LS832 Datasheet, PDF (1/1 Pages) Micross Components – Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET

LS832
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
The LS832 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS832 features a 25-
mV offset and 20-µV/°C drift.
FEATURES
ULTRA LOW DRIFT
| V _GS1‐2 / T| ≤20µV/°C
ULTRA LOW LEAKAGE
LOW NOISE
I_G = 80fA TYP.
e_n = 70nV/√Hz TYP.
LOW CAPACITANCE
C_ISS = 3pF MAX.
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
LS832 Applications:
ƒ Wideband Differential Amps
ƒ High-Speed,Temp-Compensated Single-
Ended Input Amps
ƒ High-Speed Comparators
ƒ Impedance Converters and vibrations
detectors.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BV_GSS
Breakdown Voltage
40
BV_GGO
Gate‐To‐Gate Breakdown
40
Click ^{TRANSCONDUCTANCE}
Y_fSS
Full Conduction
70
Y_fS
Typical Operation
50
|Y_FS1‐2 / Y _FS|
Mismatch
‐‐
DRAIN CURRENT
I_DSS
Full Conduction
0.5
|I_DSS1‐2 / I_DSS| Mismatch at Full Conduction
‐‐
GATE VOLTAGE
V_GS(off) or V_p
Pinchoff voltage
0.6
V_GS(on)
Operating Range
‐‐
GATE CURRENT
‐I_Gmax.
Operating
‐‐
‐I_Gmax.
High Temperature
‐‐
‐I_GSSmax.
At Full Conduction
‐‐
‐I_GSSmax.
High Temperature
5
I_GGO
Gate‐to‐Gate Leakage
‐‐
OUTPUT CONDUCTANCE
Y_OSS
Full Conduction
‐‐
Y_OS
Operating
‐‐
COMMON MODE REJECTION
CMR
‐20 log | V _GS1‐2/ V _DS|
‐‐
‐20 log | V _GS1‐2/ V _DS|
‐‐
NOISE
NF
Figure
‐‐
e_n
Voltage
‐‐
CAPACITANCE
C_ISS
Input
‐‐
C_RSS
Reverse Transfer
‐‐
C_DD
Drain‐to‐Drain
‐‐
Maximum Temperatures
Storage Temperature
‐65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐V_GSS
Gate Voltage to Drain or Source
‐V_DSO
Drain to Source Voltage
‐I_G(f)
Gate Forward Current
‐I_G
Gate Reverse Current
Maximum Power Dissipation
40V
40V
10mA
10µA
Device Dissipation @ Free Air – Total
400mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V _GS1‐2 / T| max.
| V _GS1‐2 | max.
DRIFT VS.
TEMPERATURE
OFFSET VOLTAGE
20 µV/°C V_DG=10V, I_D=30µA
T_A=‐55°C to +125°C
25
mV V_DG=10V, I_D=30µA
TYP.
MAX.
UNITS
CONDITIONS
60
‐‐
V
V_DS = 0
I_D=1nA
‐‐
‐‐
V
I _G= 1nA
I_D= 0
I_S= 0
To Buy ³⁰⁰
500
100
200
0.6
3
µmho
µmho
%
V_DG= 10V
V_DG= 10V
V_GS= 0V f = 1kHz
I_D= 30µA f = 1kHz
‐‐
10
mA
V_DG= 10V
V_GS= 0V
1
5
%
2
4.5
‐‐
4
‐‐
0.1
‐‐
0.1
‐‐
0.2
5
0.5
1
‐‐
‐‐
5
‐‐
0.5
90
‐‐
90
‐‐
‐‐
1
20
70
‐‐
3
‐‐
1.5
‐‐
0.1
V
V
pA
nA
pA
nA
pA
µmho
µmho
dB
dB
nV/√Hz
pF
pF
pF
V_DS= 10V
V_DS=10V
I_D= 1nA
I_D=30µA
V_DG= 10V I_D= 30µA
T_A= +125°C
V_DS =0
V_GS= 0V, V_GS= ‐20V, T_A= +125°C
V_GG = 20V
V_DG= 10V
V_DG= 10V
V_GS= 0V
I_D= 30µA
∆V_DS = 10 to 20V I_D=30µA
∆V_DS = 5 to 10V I_D=30µA
V_DS= 10V V_GS= 0V R_G= 10MΩ
f= 100Hz NBW= 6Hz
V_DS=10V I_D=30µA f=10Hz NBW=1Hz
V_DS= 10V, V_GS= 0V, f= 1MHz
V_DS= 10V, V_GS= 0V, f= 1MHz
V_DS= 10V, I_D=30µA
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP & SOIC (Top View)
Available Packages:
LS832 / LS832 in PDIP & SOIC
LS832 / LS832 available as bare die
Please contact Micross for full package and die dimensions
Tel: [phone]
Email: [e-mail]
Web: http://www.micross.com/distribution
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