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LS3N166 Datasheet, PDF (1/1 Pages) Micross Components – a monolithic dual enhancement mode P-Channel Mosfet | |||
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LS3N166
P-CHANNEL MOSFET
The LS3N166 is a monolithic dual enhancement mode P-Channel Mosfet
The LS3N166 is a dual enhancement mode P-Channel
Mosfet and is ideal for space constrained applications
and those requiring tight electrical matching.
FEATURES
DIRECT REPLACEMENT FOR INTERSIL LS3N166
ABSOLUTE MAXIMUM RATINGS1@ 25°C (unless otherwise noted)
The hermetically sealed TO-78 package is well suited
for high reliability and harsh environment applications.
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
â65°C to +200°C
â55°C to +150°C
(See Packaging Information).
Lead Temperature (Soldering, 10 sec.)
Maximum Power Dissipation
+300°C
LS3N166 Features:
Continuous Power Dissipation (one side)
Total Derating above 25°C
300mW
4.2 mW/°C
 Very high Input Impedance
 Low Capacitance
 High Gain
 High Gate Breakdown Voltage
 Low Threshold Voltage
MAXIMUM CURRENT
Drain Current
MAXIMUM VOLTAGES
Drain to Gate or Drain to Source2
Peak Gate to Source3
50mA
â30V
±125V
GateâGate Voltage
±80V
LS3N166 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTIC
MIN TYP.
MAX
UNITS
CONDITIONS
IGSSR
Gate Reverse Leakage Current
ââ
ââ
10
VGS = â0V
IGSSF
Gate Forward Current
ââ
ââ
â10
TA= +125°C
ââ
ââ
â25
pA
VGS = â40V
IDSS
Drain to Source Leakage Current
ââ
ââ
â200
VDS = â20V
ISDS
Source to Drain Leakage Current
ââ
ââ
â400
VSD = â20V VDB = 0
ID(on)
Drain Current âOnâ
â5.0
ââ
â30
mA
VGS(th)
Gate to Source Threshold Voltage â2.0
ââ
â5.0
V
VDS = â15V, VGS = â10V
VDS = â15V, ID = â10µA
â2.0
ââ
â5.0
VDS = VGS , ID = â10µA
rDS(on)
Drain to Source âOnâ Resistance
ââ
gfs
gos
Ciss
Crss
Click Forward Transconductance
Output Admittance
Input Capacitance
Reverse Transfer Capacitance
1500
ââ
ââ
ââ
Coss
Output Capacitance
ââ
RE(Yfs)
Common Source Forward
1200
Transconductance
ââ
300
To ââ
3000
ââ
300
ââ
3
ââ
0.7
ââ
3.0
ââ
ââ
Ω
VGS = â20V, ID = â100µA
Buy µS
VDS = â15V, ID = â10mA , f = 1kHz
pF
VDS = â15V, ID = â10mA , f = 1MHz4
µS
VDS = â15V, ID = â10mA , f = 100MHz4
MATCHING CHARACTERISTICS LS3N166
SYMBOL
LIMITS
Yfs1/Yfs2
CHARACTERISTIC
Forward Transconductance Ratio
MIN
MAX
0.90
1.0
UNITS
ns
CONDITIONS
VDS = â15V, ID = â500µA , f = MHz4
VGS1â2
Gate Source Threshold Voltage
Differential
ââ
100
mV
VDS = â15V, ID = â500µA
âVGS1â2/âT
Gate Source Threshold Voltage
ââ
100
µV/°C
Differential Change with Temperature
VDS = â15V, ID = â500µA
TA = â55°C to = +25°C
Note 1 â Absolute maSxWimIuTmCHraINtinGgsTEarSeTliCmIRitiCnUg IvTalues above which LS3N166 serviceability may be impaired.
*
Note 2 â Per Transistor
Note 3 â Device must not be tested at ±125V more than once or longer than 300ms.
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Available Packages:
Device Schematic
TO-78 (Bottom View)
SWITCHING WAVEFORM & TEST CIRCUIT
LS3N166 in TO-72
LS3N166 in bare die.
Please contact Micross for full
package and die dimensions
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
*To avoid possible damage to the device while wiring, testing, or in actual
operation, follow these procedures: To avoid the buildâup of static charge, the
leads of the devices should remain shorted together with a metal ring except
when being tested or used. Avoid unnecessary handling. Pick up devices by the
case instead of the leads. Do not insert or remove devices from circuits with the
power on, as transient voltages may cause permanant damage to the devices.
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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