LS120 Datasheet, PDF (1/1 Pages) Micross Components – Linear Systems replaces discontinued Intersil IT120

LS120
MONOLITHIC DUAL
NPN TRANSISTOR
Linear Systems replaces discontinued Intersil IT120
The LS120 is a monolithic pair of NPN transistors
mounted in a single P-DIP package. The monolithic
dual chip design reduces parasitics and gives better
performance while ensuring extremely tight matching.
The LS120 is a direct replacement for discontinued
Intersil IT120.
The 8 Pin P-DIP provides ease of manufacturing, and
the symmetrical pinout prevents improper orientation.
(See Packaging Information).
LS120 Features:
ƒ High h_fe at low current
ƒ Tight matching
ƒ Tight V_BE tracking
ƒ Low Output Capacitance
FEATURES
Direct Replacement for INTERSIL IT120
HIGH h_FE @ LOW CURRENT
OUTPUT CAPACITANCE
V_BE tracking
ABSOLUTE MAXIMUM RATINGS ¹
@ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Maximum Power Dissipation
Continuous Power Dissipation (One side)
Continuous Power Dissipation (Both sides)
Linear Derating factor (One side)
Linear Derating factor (Both sides)
Maximum Currents
Collector Current
≥ 200 @ 10µA
≤ 2.0pF
≤ 5.0µV°C
‐65°C to +200°C
‐55°C to +150°C
250mW
500mW
2.3mW/°C
4.3mW/°C
10mA
MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated)
SYMBOL
CHARACTERISTIC
MIN TYP MAX UNITS CONDITIONS
|V_BE1 – V_BE2 |
Base Emitter Voltage Differential
‐‐
‐‐
2
mV
I_C = 10µA, V_CE = 5V
∆|(V_BE1 – V_BE2)| / ∆T
Base Emitter Voltage Differential
Change with Temperature
‐‐
‐‐
5
µV/°C
I_C = 10µA, V_CE = 5V
T_A = ‐55°C to +125°C
Click To Buy ^{|IB1–IB2|}
Base Current Differential
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BV_CBO
Collector to Base Voltage
45
‐‐
‐‐
5
TYP.
MAX. UNITS
‐‐
‐‐
V
nA
I_C = 10µA, V_CE = 5V
CONDITIONS
I_C = 10µA, I_E = 0
BV_CEO
Collector to Emitter Voltage
45
‐‐
‐‐
V
BV_EBO
Emitter‐Base Breakdown Voltage
6.2
‐‐
‐‐
V
BV_CCO
Collector to Collector Voltage
60
‐‐
‐‐
V
I_C = 10µA, I_B = 0
I_E = 10µA, I_C = 0²
I_C = 10µA, I_E = 0
h_FE
DC Current Gain
200
‐‐
‐‐
I_C = 10µA, V_CE = 5V
225
‐‐
‐‐
I_C = 1.0mA, V_CE = 5V
V_CE(SAT)
Collector Saturation Voltage
‐‐
‐‐
0.5
V
I_C = 0.5mA, I_B = 0.05mA
I_EBO
Emitter Cutoff Current
‐‐
‐‐
1
nA
I_CBO
Collector Cutoff Current
‐‐
‐‐
1
nA
I_C = 0, V_EB = 3V
I_E = 0, V_CB = 45V
C_OBO
Output Capacitance
‐‐
‐‐
2
pF
I_E = 0, V_CB = 5V
C_C1C2
Collector to Collector Capacitance
‐‐
‐‐
2
pF
I_C1C2
Collector to Collector Leakage Current
‐‐
‐‐
10
nA
V_CC = 0V
V_CC = ±60V
f_T
Current Gain Bandwidth Product
220
‐‐
‐‐
MHz
I_C = 1mA, V_CE = 5V
NF
Narrow Band Noise Figure
‐‐
‐‐
3
dB
I_C = 100µA, V_CE = 5V, BW=200Hz, R_G= 10KΩ,
f = 1KHz
Notes:
1. Absolute Maximum ratings are limiting values above which serviceability may be impaired
2. The reverse base‐to‐emitter voltage must never exceed 6.2 volts; the reverse base‐to‐emitter current must never exceed 10µA.
Available Packages:
LS120 in P-DIP
LS120 available as bare die
Please contact Micross for full package and die dimensions:
Email: [e-mail]
Web: www.micross.com/distribution.aspx
P-DIP (Top View)
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.