AS5SS256K18 Datasheet, PDF (1/14 Pages) Austin Semiconductor – 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through

SSRAM
AS5SS256K18
256K x 18 SSRAM
Synchronous Burst SRAM,
Flow-Through
FEATURES
• Fast access times: 8, 10, and 15ns
• Fast clock speed: 113, 100, and 66 MHz
• Fast clock and OE\ access times
• Single +3.3V ± 5% power supply (V_DD)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRTIE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and address
pipelining
• Clock-controlled and registered addresses, data I/Os and
control signals
• Interally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• Low capacitive bus loading
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
• RoHs compliant options available
OPTIONS
• Timing
7.5ns/8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
MARKING
-8
-9
-10
• Packages
TQFP
DQ No. 1001
• Operating Temperature Ranges:
- Military -55^oC to +125^oC
/IT
- Enhanced -45^oC to +105^oC
/ET
- Industrial -45^oC to +85^oC
/XT
GENERAL DESCRIPTION
The Micross Components Synchronous Burst SRAM family
employs high-speed, low power CMOS designs that are fabricated
using an advanced CMOS process.
The 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM
core with advanced synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE\), two additional chip enables for easy depth expansion (CE2\,
PIN ASSIGNMENT
(Top View)
100-pin TQFP (DQ)
NC
NC
NC
V_DDQ
V_SS
NC
NC
DQb
DQb
V_SS
V_DDQ
DQb
DQb
NC
V_DD
NC
V_SS
DQb
DQb
V_DDQ
V_SS
DQb
DQb
DQPb
NC
V_SS
V_DDQ
NC
NC
NC
1 ^{100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81}
2
80 SA
3
79 NC
4
78 NC
5
77 V_DDQ
6
76 V_SS
7
75 NC
8
74 DQPa
9
73 DQa
10
72 DQa
11
71 V_SS
12
70 V_DDQ
13
69 DQa
14
68 DQa
15
16
67
66
V_SS
NC
17
65 V_DD
18
64 ZZ
19
63 DQa
20
62 DQa
21
61 V_DDQ
22
60 V_SS
23
59 DQa
24
58 DQa
25
57 NC
26
56 NC
27
55 V_SS
28
54 V_DDQ
29
53 NC
30
52 NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 4546 47 48 49 50 ^{51 NC}
**pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\).
Asynchronous inputs include the output enable (OE\), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. The data-out
(Q), enabled by OE\, is also asynchronous. WRITE cycles can be from
one to two bytes wide, as controlled by the write control inputs.
Burst operation can be initiated with either address status processor
(ADSP\) or address status controller (ADSC\) inputs. Subsequent
burst addresses can be internally generated as controlled by the burst
advance input (ADV\).
Address and write control are registered on-chip to simplify WRITE
cycles. This allows self-timed WRITE cycles. Individual byte enables
allow individual bytes to be written. During WRITE cycles on this
x18 device BWa\ controls DQa pins and DQPa; BWb\ controls DQb
pins and DQPb. GW\ LOW causes all bytes to be written. Parity bits
are available on this device.
The 4Mb Synchronous Burst SRAMs operate from a +3.3V V_DD
power supply, and all inputs and outputs are TTL-compatible. The
device is ideally suited for 486, Pentium®, and PowerPC systems and
those systems that benefit from a wide synchronous data bus.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
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