AS5SP512K36 Datasheet, PDF (1/12 Pages) Micross Components – On-Chip Address and Control Registers

Plastic Encapsulated Microcircuit
18Mb, 512K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
 Synchronous Operation in relation to the input Clock
 2 Stage Registers resulting in Pipeline operation
 On chip address counter (base +3) for Burst operations
 Self-Timed Write Cycles
 On-Chip Address and Control Registers
 Byte Write support
 Global Write support
 On-Chip low power mode [powerdown] via ZZ pin
 Interleaved or Linear Burst support via Mode pin
 Three Chip Enables for ease of depth expansion without
Data Contention.
 Two Cycle load, Single Cycle Deselect
 Asynchronous Output Enable (OE\)
 Three Pin Burst Control (ADSP\, ADSC\, ADV\)
 3.3V Core Power Supply
 3.3V/2.5V IO Power Supply
 JEDEC Standard 100 pin TQFP Package
 Available in Industrial, Enhanced, and Mil-
Temperature Operating Ranges
RoHs compliant options available
SSRAM
AS5SP512K36
100-PIN TQFP
PINOUT
(3-CHIP ENABLE)
Fast Access Times
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.1
3.1
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
Block Diagram
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
❑ Synchronous Pipeline
Burst
❋ Two (2) cycle load
❋ One (1) cycle
de-select
❋ One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
Units
ns
ns
ns
DQx, DQPx
GENERAL DESCRIPTION
The AS5SP512K36 is a 18Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High
Performance CMOS technology and is organized as a
512K x 36 array. It integrates address and control registers,
a two (2) bit burst address counter supporting four (4)
double-word transfers. Writes are internally self-timed and
synchronous to the rising edge of clock.
The AS5SP512K36 includes advanced control options
including Global Write, Byte Write as well as an
asynchronous output enable. Burst Cycle controls are
handled by three (3) input pins, ADV\, ADSP\ and ADSC\.
Burst operation can be initiated with either the Address
Status Processor (ADSP\) or Address Status controller
(ADSC\) inputs. Subsequent burst addresses are generated
internally in the system’s burst sequence control block and
are controlled by the Address Advance (ADV\) control
input.
AS5SP512K36
Rev. 3.0 10/13
Micross Components reserves the right to change products or specifications without notice.
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