AS5SP512K18 Datasheet, PDF (1/13 Pages) Micross Components – On chip address counter for Burst operations

Plastic Encapsulated Microcircuit
9Mb, 512K x 18, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
 Synchronous Operation in relation to the input Clock
 2 Stage Registers resulting in Pipeline operation
 On chip address counter for Burst operations
 Self-Timed Write Cycles
 On-Chip Address and Control Registers
 Byte Write support
 Global Write support
 On-Chip low power mode [powerdown] via ZZ pin
 Interleaved or Linear Burst support via Mode pin
 Three Chip Enables for ease of depth expansion
without Data Contention.
 Two Cycle load, Single Cycle Deselect
 Asynchronous Output Enable (OE\)
 Three Pin Burst Control (ADSP\, ADSC\, ADV\)
 3.3V Core Power Supply
 3.3V/2.5V IO Power Supply
 JEDEC Standard 100 pin TQFP Package
 Available in Industrial (-40^oC to +85^oC), Enhanced
(-40^oC to +105^oC), and Mil-Temperature (-55^oC to
+125^oC) Operating Ranges
 RoHS compliant options
NC
1
NC
2
NC
3
VDDQ
4
VSSQ
5
NC
6
NC
7
DQb
8
DQb
9
VSSQ
10
VDDQ
11
DQb
12
DQb
13
NC
14
VDD
15
NC
16
VSS
17
DQb
18
DQb
19
VDDQ
20
VSSQ
21
DQb
22
DQb
23
DQPb
24
NC
25
VSSQ
26
VDDQ
27
NC
28
NC
29
NC
30
SSRAM
AS5SP512K18
SSRAM [SPB]
80
A
79
NC
78
NC
77
VDDQ
76
VSSQ
75
NC
74
DQPa
73
DQa
72
DQa
71
VSSQ
70
VDDQ
69
DQa
68
DQa
67
VSS
66
NC
65
VDD
64
ZZ
63
DQa
62
DQa
61
VDDQ
60
VSSQ
59
DQa
58
DQa
57
NC
56
NC
55
VSSQ
54
VDDQ
53
NC
52
NC
51
NC
FAST ACCESS TIMES
GENERAL DESCRIPTION
Parameter
Symbol
Cycle Time
tCYC
Clock Access Time
tCD
Output Enable Access tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x18
SBP
T Synchronous Pipeline
Burst
N Two (2) cycle load
N One (1) cycle
de-select
N One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
DQx, DQPx
Micross Components AS5SP512K18 is a 9.0Mb High
Performance Synchronous Pipeline Burst SRAM, available
in multiple temperature screening levels, fabricated using
High Performance CMOS technology and is organized as
a 512K x 18. It integrates address and control registers,
a two (2) bit burst address counter supporting four (4)
double-word transfers. Writes are internally self-timed and
synchronous to the rising edge of clock.
The AS5SP512K18 includes advanced control options
including Global Write, Byte Write as well as an
Asynchronous Output enable. Burst Cycle controls
are handled by three (3) input pins, ADV\, ADSP\ and
ADSC\. Burst operation can be initiated with either the
Address Status Processor (ADSP\) or Address Status Cache
controller (ADSC\) inputs. Subsequent burst addresses are
generated internally in the system’s burst sequence control
block and are controlled by Address Advance (ADV\)
control input.
AS5SP512K18
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
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