AS5SP256K36 Datasheet, PDF (1/14 Pages) Micross Components – Global Write support

COTS PEM
SSRAM
AS5SP256K36
Plastic Encapsulated Microcircuit
9.0Mb, 256K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
DQPc
1
DQc
2
DQc
3
VDDQ
4
VSSQ
5
DQc
6
DQc
7
DQc
8
DQc
9
VSSQ
10
VDDQ
11
DQc
12
DQc
13
NC
14
VDD
15
NC
16
VSS
17
DQd
18
DQd
19
VDDQ
20
VSSQ
21
DQd
22
DQd
23
DQd
24
DQd
25
VSSQ
26
VDDQ
27
DQd
28
DQd
29
DQPd
30
SSRAM [SPB]
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package,
• Available in Industrial, Enhanced, and Mil-Temperature FAST ACCESS TIMES
Operating Ranges
Parameter
Symbol 200Mhz
• RoHs compliant options available
Cycle Time
tCYC
5.0
Clock Access Time
tCD
3.0
Output Enable Access Time tOE
3.0
166Mhz
6.0
3.5
3.5
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
133Mhz
7.5
4.0
4.0
DQP
DQb
DQb
VDD
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDD
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDD
DQa
DQa
DQP
Units
ns
ns
ns
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
❑ Synchronous Pipeline
Burst
❋ Two (2) cycle load
❋ One (1) cycle
de-select
❋ One (1) cycle latency
on Mode change
AS5SP256K36
Rev. 2.2 10/13
Output Output
Register Driver
Input
Register
GENERAL DESCRIPTION
The AS5SP256K36 is a 9.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High
Performance CMOS technology and is organized as a
256K x 36. It integrates address and control registers,
a two (2) bit burst address counter supporting four (4)
double-word transfers. Writes are internally self-timed
and synchronous to the rising edge of clock.
The AS5SP256K36 includes advanced control options
including Global Write, Byte Write as well as an
DQx, DQP _{Asynchronous Output enable. Burst Cycle controls}
are handled by three (3) input pins, ADV\, ADSP\ and
ADSC\. Burst operation can be initiated with either the
Address Strobe Processor (ADSP\) or Address Strobe
controller (ADSC\) inputs. Subsequent burst addresses
are generated internally in the system’s burst sequence
control block and are controlled by Address Advance
(ADV\) control input.
Micross Components reserves the right to change products or specifications without notice.
1