AS5C4008 Datasheet, PDF (1/17 Pages) Austin Semiconductor – 512K x 8 SRAM SRAM MEMORY ARRAY

512K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATION
• SMD 5962-95600
• SMD 5962-95613
• MIL STD-883
FEATURES
• High Speed: 12, 15, 17, 20, 25, 35 and 45ns
• High-performance, low power military grade device
• Single +5V ±10% power supply
• Easy memory expansion with CE\ and OE\ options
• All inputs and outputs are TTL-compatible
• Ease of upgradability from 1 Meg using the 32 pin
evolutionary version.
OPTIONS
MARKING
• Timing
12ns access
-12
15ns access
-15
17ns access
-17
20ns access
-20
25ns access
-25
35ns access
-35
45ns access
-45
• Operating Temperature Range
Military: -55^oC to +125^oC
XT
Industrial: -40^oC to +85^oC
IT
• Packages
Ceramic Dip (600 mil)
CW No. 112
Ceramic Flatpack
F
No. 304
Ceramic LCC
EC
No. 209
Ceramic SOJ
ECJ No. 502
• Options
2V data retention/ low power
L
NOTE: Not all combinations of operating temperature, speed, data retention and
low power are necessarily available. Please contact factory for availability of specific
part number combinations.
SRAM
AS5C4008
PIN ASSIGNMENT
(Top View)
32-Pin DIP (CW), 32-Pin LCC (EC)
32-Pin SOJ (ECJ)
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
Vss 16
32 Vcc
31 A15
30 A17
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
32-Pin Flat Pack (F)
A18
1
32
Vcc
A16
2
31
A15
A14
3
30
A17
A12
4
29
WE\
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE\
A2
10
23
A10
A1
11
22
CE\
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
Vss
16
17
I/O3
GENERAL DESCRIPTION
The AS5C4008 is a 4 megabit monolithic CMOS SRAM, orga-
nized as a 512K x 8.
The evolutionary 32 pin device allows for easy upgrades from
the 1 meg SRAM.
For flexibility in high-speed memory applications, Micross of-
fers chip enable (CE\) and output enable (OE\) capabilities. These
enhancements can place the outputs in High-Z for additional flexibility
in system design.
Writing to these devices is accomplished when write enable
(WE\) and CE\ inputs are both LOW. Reading is accomplished when
WE\ remains HIGH and CE\ and OE\ go LOW. This allows systems
designers to meet low standby power requirements.
All devices operate from a single +5V power supply and all inputs
are fully TTL-Compatible.
AS5C4008
Rev. 6.4 01/10
1
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please visit our web site at
www.micross.com
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