3N165 Datasheet, PDF (1/1 Pages) Calogic, LLC – Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier

3N165
P-CHANNEL MOSFET
The 3N165 is a monolithic dual enhancement mode P-Channel Mosfet
The 3N165 is a dual enhancement mode P-Channel
Mosfet and is ideal for space constrained applications
and those requiring tight electrical matching.
FEATURES
DIRECT REPLACEMENT FOR INTERSIL 3N165
ABSOLUTE MAXIMUM RATINGS¹@ 25°C (unless otherwise noted)
The hermetically sealed TO-78 package is well suited
for high reliability and harsh environment applications.
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
‐65°C to +200°C
‐55°C to +150°C
(See Packaging Information).
Lead Temperature (Soldering, 10 sec.)
Maximum Power Dissipation
+300°C
3N165 Features:
Continuous Power Dissipation (one side)
Total Derating above 25°C
300mW
4.2 mW/°C
ƒ Very high Input Impedance
ƒ Low Capacitance
ƒ High Gain
ƒ High Gate Breakdown Voltage
ƒ Low Threshold Voltage
MAXIMUM CURRENT
Drain Current
MAXIMUM VOLTAGES
Drain to Gate or Drain to Source²
Peak Gate to Source³
50mA
‐40V
±125V
Gate‐Gate Voltage
±80V
3N165 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTIC
MIN TYP.
MAX
UNITS
CONDITIONS
I_GSSR
Gate Reverse Leakage Current
‐‐
‐‐
10
V_GS = ‐0V
I_GSSF
Gate Forward Current
‐‐
‐‐
‐10
T_A= +125°C
‐‐
‐‐
‐25
pA
V_GS = ‐40V
I_DSS
Drain to Source Leakage Current
‐‐
‐‐
‐200
V_DS = ‐20V
I_SDS
Source to Drain Leakage Current
‐‐
‐‐
‐400
V_SD = ‐20V V_DB = 0
I_D(on)
Drain Current “On”
‐5.0
‐‐
‐30
mA
V_GS(th)
Gate to Source Threshold Voltage ‐2.0
‐‐
‐5.0
V
V_DS = ‐15V, V_GS = ‐10V
V_DS = ‐15V, I_D = ‐10µA
‐2.0
‐‐
‐5.0
V_DS = V_GS , I_D = ‐10µA
r_DS(on)
Drain to Source “On” Resistance
‐‐
g_fs
g_os
C_iss
C_rss
Click Forward Transconductance
Output Admittance
Input Capacitance
Reverse Transfer Capacitance
1500
‐‐
‐‐
‐‐
C_oss
Output Capacitance
‐‐
R_E(Y_fs)
Common Source Forward
1200
Transconductance
‐‐
300
To ^‐‐
3000
‐‐
300
‐‐
3
‐‐
0.7
‐‐
3.0
‐‐
‐‐
Ω
V_GS = ‐20V, I_D = ‐100µA
Buy ^µS
V_DS = ‐15V, I_D = ‐10mA , f = 1kHz
pF
V_DS = ‐15V, I_D = ‐10mA , f = 1MHz⁴
µS
V_DS = ‐15V, I_D = ‐10mA , f = 100MHz⁴
MATCHING CHARACTERISTICS 3N165
SYMBOL
LIMITS
Y_fs1/Y_fs2
CHARACTERISTIC
Forward Transconductance Ratio
MIN
MAX
0.90
1.0
UNITS
ns
CONDITIONS
V_DS = ‐15V, I_D = ‐500µA , f = MHz⁴
V_GS1‐2
Gate Source Threshold Voltage
Differential
‐‐
100
mV
V_DS = ‐15V, I_D = ‐500µA
∆V_GS1‐2/∆T
Gate Source Threshold Voltage
‐‐
100
µV/°C
Differential Change with Temperature
V_DS = ‐15V, I_D = ‐500µA
T_A = ‐55°C to = +25°C
Note 1 ‐ Absolute ma^Sx^Wim^Iu^Tm^CHra^INtin^Ggs^TEar^Se^Tli^Cm^IRiti^Cn^Ug ^Iv^Talues above which 3N165 serviceability may be impaired. *
Note 2 – Per Transistor
Note 3 – Device must not be tested at ±125V more than once or longer than 300ms.
Note 4 – For design reference only, not 100% tested
SWITCHING WAVEFORM & TEST CIRCUIT
Available Packages:
Device Schematic
TO-78 (Bottom View)
3N165 in TO-72
3N165 in bare die.
Please contact Micross for full
package and die dimensions
Tel: [phone]
Email: [e-mail]
Web: http://www.micross.com/distribution
*To avoid possible damage to the device while wiring, testing, or in actual
operation, follow these procedures: To avoid the build‐up of static charge, the
leads of the devices should remain shorted together with a metal ring except
when being tested or used. Avoid unnecessary handling. Pick up devices by the
case instead of the leads. Do not insert or remove devices from circuits with the
power on, as transient voltages may cause permanant damage to the devices.
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.