2N3958 Datasheet, PDF (1/1 Pages) InterFET Corporation – N-Channel Dual Silicon Junction Field-Effect Transistor

2N3958
MONOLITHIC DUAL
N-CHANNEL JFET
The 2N3958 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
The 2N3958 family are matched JFET pairs for
differential amplifiers. The 2N3958 family of general
purpose JFETs is characterized for low and medium
frequency differential amplifiers requiring low offset
voltage, drift, noise and capacitance
The 2N3958 family exhibits low capacitance - 6pF max
and a spot noise figure of - 0.5dB max. The part offers
a superior tracking ability.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
FEATURES
LOW DRIFT
LOW LEAKAGE
LOW NOISE
ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
|∆ V_GS1‐2 /∆T|= 5µV/°C max.
I_G = 20pA TYP.
e_n = 10nV/√Hz TYP.
Maximum Temperatures
Storage Temperature
‐65°C to +200°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐V_GSS
Gate Voltage to Drain or Source
‐V_DSO
Drain to Source Voltage
‐I_G(f)
Gate Forward Current
Maximum Power Dissipation
60V
60V
50mA
Device Dissipation @ Free Air – Total
400mW @ 25°C
2N3958 Applications:
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
ƒ Wideband Differential Amps
ƒ High Input Impedance Amplifiers
SYMBOL
| V _GS1‐2 / T| max.
| V _GS1‐2 | max.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
CHARACTERISTICS
DRIFT VS.
TEMPERATURE
OFFSET VOLTAGE
VALUE
100
25
UNITS
µV/°C
mV
CONDITIONS
V_DG=20V, I_D=200µA
T_A=‐55°C to +125°C
V_DG=20V, I_D=200µA
SYMBOL
CHARACTERISTICS
MIN.
TYP.
MAX.
UNITS
CONDITIONS
BV_GSS
Breakdown Voltage
60
‐‐
‐‐
V
V_DS = 0
I_D=1µA
BV_GGO
Gate‐To‐Gate Breakdown
60
‐‐
‐‐
V
I _G= 1nA
I_D= 0
I_S= 0
TRANSCONDUCTANCE
Y_fSS
Full Conduction
1000
Click ^YfS
Typical Operation
500
|Y_FS1‐2 / Y _FS|
Mismatch
‐‐
DRAIN CURRENT
I_DSS
Full Conduction
0.5
|I_DSS1‐2 / I_DSS| Mismatch at Full Conduction
‐‐
GATE VOLTAGE
2000
3000
µmho
V_DG= 20V V_GS= 0V f = 1kHz
To Buy ⁷⁰⁰
1000
0.6
3
2
5
1
5
µmho
%
mA
%
V_DG= 20V I_D= 200µA
V_DG= 20V
V_GS= 0V
V_GS(off) or V_p
Pinchoff voltage
1
V_GS(on)
Operating Range
0.5
GATE CURRENT
‐I_G
Operating
‐‐
‐I_G
High Temperature
‐‐
‐I_G
Reduced V_DG
‐‐
‐I_GSS
At Full Conduction
‐‐
OUTPUT CONDUCTANCE
2
4.5
‐‐
4
20
50
‐‐
50
5
‐‐
‐‐
100
V
V_DS= 20V
I_D= 1nA
V
V_DS=20V
I_D=200µA
pA
V_DG= 20V I_D= 200µA
nA
T_A= +125°C
pA
V_DG= 10V I_D= 200µA
pA
V_DG= 20V
V_DS= 0
Y_OSS
Full Conduction
‐‐
Y_OS
Operating
‐‐
|Y_OS1‐2|
Differential
‐‐
COMMON MODE REJECTION
CMR
‐20 log | V_GS1‐2/ V_DS|
‐‐
CMR
‐20 log | V_GS1‐2/ V_DS|
‐‐
NOISE
NF
Figure
‐‐
‐‐
5
0.1
1
0.01
0.1
100
‐‐
75
‐‐
‐‐
0.5
µmho
µmho
µmho
dB
dB
dB
V_DG= 20V
V_DG= 20V
V_GS= 0V
I_D= 200µA
∆V_DS = 10 to 20V I_D=200µA
∆V_DS = 5 to 10V I_D=200µA
V_DS= 20V V_GS= 0V R_G= 10MΩ
f= 100Hz NBW= 6Hz
e_n
Voltage
‐‐
‐‐
15
nV/√Hz
V_DS=20V I_D=200µA f=10Hz NBW=1Hz
CAPACITANCE
C_ISS
Input
‐‐
‐‐
6
pF
V_DS= 20V V_GS= 0V f= 1MHz
C_RSS
Reverse Transfer
‐‐
‐‐
2
pF
C_DD
Drain‐to‐Drain
‐‐
0.1
‐‐
pF
V_DG= 20V
I_D= 200µA
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP / SOIC (Top View)
Micross Components Europe
Available Packages:
2N3958 in PDIP / SOIC
2N3958 available as bare die
Please contact Micross for full package and die dimensions
Tel: [phone]
Email: [e-mail]
Web: http://www.micross.com/distribution
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