A42MX09-FPL84 Datasheet, PDF (86/142 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
TTL Output Module Timing⁵
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t_ENLZ
t_GLH
t_GHL
t_LSU
t_LH
t_LCO
Enable Pad LOW to Z
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Output Set-Up
I/O Latch Output Hold
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
6.9
7.6
8.7
10.2
14.3 ns
4.9
5.5
6.2
7.3
10.2 ns
4.9
5.5
6.2
7.3
10.2 ns
0.7
0.7
0.8
1.0
1.4
ns
0.0
0.0
0.0
0.0
0.0
ns
7.9
8.8
10.0
11.8
16.5 ns
t_ACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.9
12.1
13.7
16.1
22.5 ns
d_TLH
Capacitive Loading, LOW to HIGH
d_THL
Capacitive Loading, HIGH to LOW
CMOS Output Module Timing⁵
0.10
0.11
0.10
0.11
0.12
0.12
0.14
0.20 ns/pF
0.14
0.20 ns/pF
t_DLH
t_DHL
t_ENZH
t_ENZL
t_ENHZ
t_ENLZ
t_GLH
t_GHL
t_LSU
t_LH
t_LCO
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Set-Up
I/O Latch Hold
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
4.9
5.5
6.2
7.3
10.3 ns
3.4
3.8
4.3
5.1
7.1 ns
3.7
4.1
4.7
5.5
7.7 ns
4.1
4.6
5.2
6.1
8.5 ns
7.4
8.2
9.3
10.9
15.3 ns
6.9
7.6
8.7
10.2
14.3 ns
7.0
7.8
8.9
10.4
14.6 ns
7.0
7.8
8.9
10.4
14.6 ns
0.7
0.7
0.8
1.0
1.4
ns
0.0
0.0
0.0
0.0
0.0
ns
7.9
8.8
10.0
11.8
16.5 ns
Notes:
1. For dual-module macros, use t_PD1 + t_RD1 + t_PDn, t_CO + t_RD1 + t_PDn, or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-82
Revision 11