A40MX04-PLG68 Datasheet, PDF (83/142 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J = 70°C)
–3 Speed –2 Speed –1 Speed
Std Speed –F Speed
Parameter / Description
Logic Module Combinatorial Functions¹
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t_PD
Internal Array Module Delay
t_PDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays²
1.9
2.1
2.3
2.7
3.8 ns
2.2
2.5
2.8
3.3
4.7 ns
t_RD1
FO = 1 Routing Delay
t_RD2
FO = 2 Routing Delay
t_RD3
FO = 3 Routing Delay
t_RD4
FO = 4 Routing Delay
t_RD5
FO = 8 Routing Delay
t_RDD
Decode-to-Output Routing Delay
Logic Module Sequential Timing^{3, 4}
1.3
1.5
1.7
2.0
2.7 ns
1.8
2.0
2.3
2.7
3.7 ns
2.3
2.5
2.8
3.4
4.7 ns
2.8
3.1
3.5
4.1
5.7 ns
4.6
5.2
5.8
6.9
9.6 ns
0.5
0.5
0.6
0.7
1.0 ns
t_CO
Flip-Flop Clock-to-Output
1.8
2.0
2.3
2.7
3.7 ns
t_GO
Latch Gate-to-Output
1.8
2.0
2.3
2.7
3.7 ns
t_SUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
t_HD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
t_RO
Flip-Flop (Latch) Reset-to-Output
2.2
2.4
2.7
3.2
4.5 ns
t_SUENA Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
t_HENA Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t_WCLKA Flip-Flop (Latch)
Clock Active Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
t_WASYN Flip-Flop (Latch)
Asynchronous Pulse Width
6.1
6.8
7.7
9.0
12.6
ns
Synchronous SRAM Operations
t_RC
Read Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
t_WC
Write Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
t_RCKHL Clock HIGH/LOW Time
4.8
5.3
6.0
7.0
9.8
ns
t_RCO
Data Valid After Clock HIGH/LOW
4.8
5.3
6.0
7.0
9.8 ns
t_ADSU Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
Notes:
1. For dual-module macros, use t_PD1 + t_RD1 + t_PDn, t_CO + t_RD1 + t_PDn, or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 11
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