A3PN125-ZVQG100 Datasheet, PDF (54/114 Pages) Microsemi Corporation – ProASIC3 nano Flash FPGAs

ProASIC3 nano DC and Switching Characteristics
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
Data
Enable
CLK
CLR
DOUT
CC
D
Q
DFN1E1C1
Y
EE
Core
Array
Data_out ^FF
D
Q
DFN1E1C1
GG
E
E
EOUT
BB
CLR
CLR
LL
HH
AA
DD
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
INBUF
JJ
D
Q
DFN1E1C1
KK
E
CLR
INBUF
CLKBUF
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
Figure 2-11 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
2-40
Revision 11