A3PE1500-FGG484 Datasheet, PDF (53/162 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs with Optional Soft ARM Support

ProASIC3E Flash Family FPGAs
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-51 • Minimum and Maximum DC Input and Output Levels
2.5 GTL
VIL
VIH
VOL VOH IOL IOH IOSL
IOSH IIL IIH
Drive
Strength
20 mA³
Min.,
Max.
Min.
V
V
V
–0.3 VREF – 0.05 VREF + 0.05
Max.
V
3.6
Max.
V
0.4
Min.
V mA mA
– 20 20
Max.
mA¹
124
Max.
mA¹
169
µA² µA²
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-13 • AC Loading
Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring
Point* (V)
VREF (typ.) (V) VTT (typ.) (V)
VREF – 0.05
VREF + 0.05
0.8
0.8
1.2
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
C_LOAD (pF)
10
Timing Characteristics
Table 2-53 • 2.5 V GTL
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed
Grade
Std.
t_DOUT
0.60
t_DP
2.13
t_DIN
0.04
t_PY
2.46
t_EOUT
0.43
t_ZL
2.16
t_ZH
t_LZ t_HZ
2.13
t_ZLS
4.40
t_ZHS
4.36
Units
ns
–1
0.51 1.81 0.04 2.09 0.36 1.84 1.81
3.74 3.71
ns
–2
0.45 1.59 0.03 1.83 0.32 1.61 1.59
3.28 3.26
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
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