A1440A-1VQ100C Datasheet, PDF (29/90 Pages) Microsemi Corporation – Accelerator Series FPGAs – ACT 3 Family

Accelerator Series FPGAs – ACT 3 Family
Timing Derating
ACT 3 devices are manufactured in a CMOS process. Therefore, device performance varies according
to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature, and worst-case processing.
Table 2-15 • Timing Derating Factor (Temperature and Voltage)
(Commercial Minimum/Maximum Specification) x
Industrial
Military
Min.
Max.
Min. Max.
0.66
1.07
0.63
1.17
Table 2-16 • Timing Derating Factor for Designs at Typical Temperature (T_J = 25°C)
and Voltage (5.0 V)
(Commercial Maximum Specification) x
0.85
Table 2-17 • Temperature and Voltage Derating Factors
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
–55
–40
0
25
70
85
4.50
0.72
0.76
0.85
0.90
1.04
1.07
4.75
0.70
0.73
0.82
0.87
1.00
1.03
5.00
0.68
0.71
0.79
0.84
0.97
1.00
5.25
0.66
0.69
0.77
0.82
0.94
0.97
5.50
0.63
0.66
0.74
0.79
0.90
0.93
125
1.117
1.12
1.09
1.06
1.01
1.20
1.10
1.00
0.90
0.80
0.70
0.60
4.50
4.75
5.00
5.25
5.50
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 2-18 • Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
Revision 3
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