A3PN060-ZVQG100 Datasheet, PDF (26/114 Pages) Microsemi Corporation – ProASIC3 nano Flash FPGAs

ProASIC3 nano DC and Switching Characteristics
User I/O Characteristics
Timing Model
Input LVCMOS 2.5 V
I/O Module
(Registered)
t_PY = 1.04 ns
DQ
Input LVTTL
Clock
tt_IISCULKDQ==00.2.264nnss
t_PY = 0.84 ns
I/O Module
(Non-Registered)
LVCMOS 1.5 V
t_PY = 1.14 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
t_PD = 0.56 ns
Combinational Cell
Combinational Cell
Y
t_PD = 0.49 ns
t_DP = 2.25 ns
I/O Module
(Non-Registered)
LVCMOS 2.5V Output Drive
Strength = 8 mA High Slew Rate
Y
LVTTLOHiugthpustledwrivreatsetrength ^{= 4 mA}
t_PD = 0.87 ns
t_DP = 2.87 ns
Combinational Cell
I/O Module
(Non-Registered)
Y
t_PD = 0.51 ns
Combinational Cell
t_DP = 2.21 ns
LVTTLOHiugthpustledwrivreatsetrength ^{= 8 mA}
I/O Module
(Non-Registered)
Y
t_PD = 0.47 ns
t_DP = 3.02 ns
LVCMOS 1.5 V Output drive strength = 2 mA
High slew rate
Register Cell _{Combinational Cell Register Cell}
DQ
Y
DQ
t_PD = 0.47 ns
I/O Module
(Registered)
DQ
LVTTL 3.3 V Output drive
strength = 8 mA High slew rate
t_DP = 2.21 ns
t_CLKQ = 0.55 ns
t_SUD = 0.43 ns
Input LVTTL
Clock
t_CLKQ = 0.55 ns
t_SUD = 0.43 ns
Input LVTTL
Clock
t_OCLKQ = 0.59 ns
t_OSUD = 0.31 ns
t_PY = 0.84 ns
t_PY = 0.84 ns
Figure 2-2 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (T_J = 70°C), Worst Case
VCC = 1.425 V, with Default Loading at 10 pF
2-12
Revision 11