A1280A-1PQ160I Datasheet, PDF (25/54 Pages) Microsemi Corporation – ACT 2 Family FPGAs

ACT 2 Family FPGAs
A1280A Timing Characteristics (continued)
Table 2-19 • A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, T_J = 70°C
I/O Module Input Propagation Delays
–2 Speed
–1 Speed
Std. Speed Units
Parameter/Description
Min. Max. Min. Max. Min. Max.
t_INYH
Pad to Y High
t_INYL
Pad to Y Low
t_INGH
G to Y High
t_INGL
G to Y Low
Input Module Predicted Input Routing Delays^*
2.9
3.3
3.8 ns
2.7
3.0
3.5 ns
5.0
5.7
6.6 ns
4.8
5.4
6.3 ns
t_IRD1
FO = 1 Routing Delay
t_IRD2
FO = 2 Routing Delay
t_IRD3
FO = 3 Routing Delay
t_IRD4
FO = 4 Routing Delay
t_IRD8
FO = 8 Routing Delay
Global Clock Network
4.6
5.1
6.0 ns
5.2
5.9
6.9 ns
5.6
6.3
7.4 ns
6.5
7.3
8.6 ns
9.4
10.5
12.4 ns
t_CKH
Input Low to High
FO = 32
FO = 256
10.2
13.1
11.0
14.6
12.8 ns
17.2
t_CKL
Input High to Low
FO = 32
FO = 256
10.2
13.3
11.0
14.9
12.8 ns
17.5
t_PWH
Minimum Pulse Width High
FO = 32 5.0
5.5
6.6
ns
FO = 256 5.8
6.4
7.6
t_PWL
Minimum Pulse Width Low
FO = 32 5.0
5.5
6.6
ns
FO = 256 5.8
6.4
7.6
t_CKSW Maximum Skew
FO = 32
0.5
0.5
0.5 ns
FO = 256
2.5
2.5
2.5
t_SUEXT Input Latch External Setup
FO = 32 0.0
0.0
0.0
ns
FO = 256 0.0
0.0
0.0
t_HEXT
Input Latch External Hold
FO = 32 7.0
7.0
7.0
ns
FO = 256 11.2
11.2
11.2
t_P
Minimum Period
FO = 32 9.6
11.2
13.3
ns
FO = 256 10.6
12.6
15.3
f_MAX
Maximum Frequency
FO = 32
105.0
90.0
FO = 256
95.0
80.0
75.0 ns
65.0
Note:
*These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-
route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
A1280A Timing Characteristics (continued)
Revision 8
2- 19