A3P250-FG256 Datasheet, PDF (23/220 Pages) Microsemi Corporation – 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

ProASIC3 Flash Family FPGAs
Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings ¹
Applicable to Standard I/O Banks
Single-Ended
C_LOAD (pF)
VCCI (V)
Static Power
PDC3 (mW) ²
Dynamic Power
PAC10 (µW/MHz) ³
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
3.3 V LVCMOS Wide Range⁴
35
3.3
–
431.08
–
431.08
2.5 V LVCMOS
35
2.5
–
247.36
1.8 V LVCMOS
35
1.8
–
128.46
1.5 V LVCMOS (JESD8-11)
35
1.5
–
89.46
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. P_DC3 is the static power (where applicable) measured on VCCI.
3. P_AC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 13
2-9