A1225A-PQ100I Datasheet, PDF (23/54 Pages) Microsemi Corporation – Up to 8,000 Gate Array Gates(20,000 PLD equivalent gates)

ACT 2 Family FPGAs
A1240A Timing Characteristics (continued)
Table 2-17 • A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, T_J = 70°C
TTL Output Module Timing¹
–2 Speed
–1 Speed
Std. Speed
Parameter/Description
Min. Max. Min. Max. Min. Max.
t_DLH
Data to Pad High
t_DHL
Data to Pad Low
t_ENZH
Enable Pad Z to High
t_ENZL
Enable Pad Z to Low
t_ENHZ
Enable Pad High to Z
t_ENLZ
Enable Pad Low to Z
t_GLH
G to Pad High
t_GHL
G to Pad Low
d_TLH
Delta Low to High
d_THL
Delta High to Low
CMOS Output Module Timing¹
8.0
9.0
10.6
10.1
11.4
13.4
8.9
10.0
11.8
11.7
13.2
15.5
7.1
8.0
9.4
8.4
9.5
11.1
9.0
10.2
11.9
11.2
12.7
14.9
0.07
0.08
0.09
0.12
0.13
0.16
t_DLH
Data to Pad High
10.2
11.5
13.5
t_DHL
Data to Pad Low
8.4
9.6
11.2
t_ENZH
Enable Pad Z to High
8.9
10.0
11.8
t_ENZL
Enable Pad Z to Low
11.7
13.2
15.5
t_ENHZ
Enable Pad High to Z
7.1
8.0
9.4
t_ENLZ
Enable Pad Low to Z
8.4
9.5
11.1
t_GLH
G to Pad High
9.0
10.2
11.9
t_GHL
G to Pad Low
11.2
12.7
14.9
d_TLH
Delta Low to High
0.12
0.13
0.16
d_THL
Delta High to Low
0.09
0.10
0.12
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
Revision 8
2- 17