A3PE1500-FG484 Datasheet, PDF (157/162 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs with Optional Soft ARM Support

Revision
v2.0
(continued)
Advance v0.6
(January 2007)
Advance v0.5
(April 2006)
ProASIC3E Flash Family FPGAs
Changes
Page
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was 3-5
updated.
Table 3-5 • Package Thermal Resistivities was updated.
3-5
Table 3-10 • Different Components Contributing to the Dynamic Power 3-8
Consumption in ProASIC3E Devices was updated.
t_WRO and t_CCKH were added to Table 3-94 • RAM4K9 and Table 3-74 to
3-95 • RAM512X18.
3-74
The note in Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-23
Figure 3-43 • Write Access After Write onto Same Address, Figure 3-44 • Read 3-71 to 3-
Access After Write onto Same Address, and Figure 3-45 • Write Access After 73
Read onto Same Address are new.
Figure 3-53 • Timing Diagram was updated.
3-80
Notes were added to the package diagrams identifying if they were top or bottom N/A
view.
The A3PE1500 "208-Pin PQFP" table is new.
4-4
The A3PE1500 "484-Pin FBGA" table is new.
4-18
The A3PE1500 "A3PE1500 Function" table is new.
4-24
In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was
ii
changed for the FG484 and FG676 packages.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
Figure 2-8 • Very-Long-Line Resources was updated.
The footnotes in Figure 2-27 • CCC/PLL Macro were updated.
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
Figure 2-8 • Very-Long-Line Resources was updated.
The footnotes in Figure 2-27 • CCC/PLL Macro were updated.
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
The "WCLK and RCLK" section was updated.
N/A
2-8
2-28
2-24
2-21
2-25
2-25
2-25
2-27
N/A
N/A
2-8
2-28
2-24
2-21
2-25
2-25
Revision 13
5-7