A3P250L-VQ100I Datasheet, PDF (154/242 Pages) Microsemi Corporation – ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

ProASIC3L DC and Switching Characteristics
Timing Characteristics
Table 2-214 • RAM4K9 – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–1 Std. Units
t_AS
t_AH
t_ENS
t_ENH
t_BKS
t_BKH
t_DS
t_DH
t_CKQ1
Address setup time
Address hold time
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
Input data (DIN) hold time
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
0.25 0.30 ns
0.00 0.00 ns
0.15 0.17 ns
0.10 0.12 ns
0.24 0.28 ns
0.02 0.02 ns
0.19 0.22 ns
0.00 0.00 ns
1.82 2.14 ns
2.40 2.83 ns
t_CKQ2
Clock High to new data valid on DOUT (pipelined)
0.91 1.07 ns
t_C2CWWL1 Address collision clk-to-clk delay for reliable write after write on same address – 0.24 0.29 ns
applicable to closing edge
t_C2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same 0.20 0.24 ns
address – applicable to opening edge
t_C2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same 0.25 0.30 ns
address – applicable to opening edge
t_RSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to data out Low on DOUT (pipelined)
0.94 1.11 ns
0.94 1.11 ns
t_REMRSTB RESET removal
0.29 0.34 ns
t_RECRSTB RESET recovery
1.53 1.80 ns
t_MPWRSTB RESET minimum pulse width
0.55 0.64 ns
t_CYC
Clock cycle time
5.10 5.87 ns
F_MAX
Maximum frequency
196 170 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-138
Revision 13