A3P1000-FG484I Datasheet, PDF (117/212 Pages) Microsemi Corporation – Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology

Output Enable Register
CLK
D_Enable
50%
1
50%
t_OESUD t_OEHD
50% 0 50%
50%
Military ProASIC3/EL Low Power Flash FPGAs
50%
t_OECKMPWH t_OECKMPWL
50%
50%
50%
Enable
Preset
Clear
EOUT
50%
t_OESUEt_OEHE
t_OEWPRE
50%
t_OERECPRE
50%
t_OEWCLR t_OERECCLR
50%
50%
t_OEPRE2Q
50% 50%
t_OECLKQ
t_OECLR2Q
50%
Figure 2-33 • Output Enable Register Timing Diagram
t_OEREMPRE
50%
t_OEREMCLR
50%
Revision 3
2- 103