LX13088 Datasheet, PDF (11/12 Pages) Microsemi Corporation – Dual 1A Step-Down Converters

LX13088
TM
®
Dual 1A Step-Down Converters
PRODUCTION DATASHEET
OPERATION
E/S DECODER LOGIC
The total power dissipated by the LX13088 device, P_TOTAL,
The E/S pin serves a dual purpose. It will enable the IC if it ^{will be comprised of the power dissipated by the RMS current}
detects either a valid clock signal or a static high logic level. A ^{flowing through the internal high-side FET during the duty}
static low logic level for longer than 4µs is determined to be a ^{cycle D time, by the RMS current flowing through the}
shutdown signal. The decode logic is shown below. The One- ^{synchronous rectifier during 1-D time, by the switching or}
shot function will produce a logic high output (Clock Detect) as ^{transitioning of the FET, and of the power dissipated by the}
long as the E/S pin is toggling. Clock Detect is used to keep ^{device supply current.}
ENABLE high and to select the E/S clock as the system clock.
If E/S is a static high (non-toggling) input, the retriggerable
one-shot will go low after 4µs; this will set Clk Det low and
INDUCTOR SELECTION
select the internal oscillator as the system clock.
A 3.3µH ±20% inductor is suggested as the internal
compensation has been optimized around this inductor value. A
3.3µH is a good compromise, since for an output voltage
ranging from VOUT = 1V to VOUT = 4V, loaded at 1A, the
LIR or the ratio of inductor ripple current to output load will
range from about 20% to 30%, assuming VIN = 5V and the
converter switching at 1.3MHz.
OUTPUT CAPACITOR
To ensure stability and good load transient response, use at
least a 10µF output capacitor for converter 1, and a 20µF or
greater for converter 2. Output ceramics capacitors with low
ESR are suitable.
SETTING THE OUTPUT VOLTAGE
SYNCHRONIZATION
The LX13088 converter’s maximum duty cycle is
approximately 90%. For a 5V input, 90% duty cycle will be
The converters can be synchronized to an external system _{achieved for an output voltage of about 4V loaded at 1A.}
clock present at the E/S input pin. During synchronization, the
converter’s switching frequency will be ½ the frequency of the
external clock, and the two converters will still be 180 degrees ^{To set the output voltage, connect a resistive divider from the}
out of phase. The lock in frequency for synchronization is ^{output to the FBx pin to signal ground. Note that the feedback}
specified to be between 1.5MHz to 3MHz, minimum sync pulse ^{voltage is 1.0V. For the desired output voltage VOUT, the}
width is 100ns.
upper resistor from VOUT to FB (R_UPPER) is calculated by the
following equation:
OVER TEMPERATURE PROTECTION
If an over temperature fault occurs, the DC-DC converter will
stop switching and the SW# outputs will become high
R
UPPER ^=R
LOWER^{×⎜⎝⎛}
VOUT
VFB
−
1⎟⎞
⎠
impedance. Note that the temperature fault occurs at a die _{RLOWER, or the resistor from FBx pin to ground, is selected to be}
temperature of approximately 160˚C. When the IC cools down, _{20kΩ. VFB = 1V, and VOUT is chosen by the designer for the}
it will attempt to resume switching. If a POR is activated as a _{given application.}
result of the OT situation, restart will be subject to the soft
start/sequencing routine and will not occur until the OT
condition has been corrected.
The device junction temperature is a function of the device’s
total power dissipation, the junction to ambient thermal
resistance, and the ambient temperature:
( ) TJ = TA + PTOTAL × θ_JA
Copyright © 2010
Rev. 1.1, 2010-06-08
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: [phone]
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