A3P030-VQG100 Datasheet, PDF (106/220 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 DC and Switching Characteristics
Timing Waveforms
CLK
[R|W]ADDR
BLK
WEN
DOUT|RD
t_CKH
t_CYC
t_CKL
t_AS
tAH
A0
A1
t_BKS
t_ENS
t_CKQ1
D_n
D₀
t_DOH1
A2
t_BKH
t_ENH
D₁
D₂
Figure 2-30 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.
CLK
[R|W]ADDR
BLK
WEN
DOUT|RD
t_CKH
t_CYC
t_CKL
t
AS
t_AH
A0
A1
t_BKS
t_ENS
t_CKQ2
D_n
A2
t_BKH
t_ENH
D₀
D₁
t_DOH2
Figure 2-31 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
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Revision 13