A3PN030-ZVQG100 Datasheet, PDF (1/114 Pages) Microsemi Corporation – ProASIC3 nano Flash FPGAs

Revision 11
ProASIC3 nano Flash FPGAs
Features and Benefits
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)^†
• FlashLock^® Designed to Secure FPGA Contents
Low Power
• Low Power ProASIC^®3 nano Products
• 1.5 V Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate^† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL^†
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)^†
• True Dual-Port SRAM (except ×18 organization)^†
Enhanced Commercial Temperature Range
• –20°C to +70°C
Table 1 • ProASIC3 nano Devices
ProASIC3 nano Devices
A3PN010 A3PN015¹ A3PN020
A3PN060 A3PN125
ProASIC3 nano-Z Devices¹
A3PN030Z^1,2 A3PN060Z¹ A3PN125Z¹
System Gates
10,000
15,000 20,000
30,000
60,000
125,000
Typical Equivalent Macrocells
86
128
172
256
512
1,024
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)²
4,608-Bit Blocks²
260
384
520
768
1,536
3,072
–
–
–
–
18
36
–
–
–
–
4
8
FlashROM Kbits
Secure (AES) ISP²
Integrated PLL in CCCs²
1
1
1
1
1
1
–
–
–
–
Yes
Yes
–
–
–
–
1
1
VersaNet Globals
4
4
4
6
18
18
I/O Banks
2
3
3
2
2
2
Maximum User I/Os (packaged device)
34
49
49
77
71
71
Maximum User I/Os (Known Good Die)
34
–
52
83
71
71
Package Pins
QFN
VQFP
QN48
QN68
QN68 QN48, QN68
VQ100
VQ100
VQ100
Notes:
1. Not recommended for new designs.
2. A3PN030Z and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets.
A3PN250
A3N250Z¹
250,000
2,048
6,144
36
8
1
Yes
1
18
4
68
68
VQ100
† A3PN030 and smaller devices do not support this feature.
January 2013
I
© 2013 Microsemi Corporation