VDP31XXB Datasheet, PDF (42/72 Pages) Micronas – Video Processor Family

VDP 31xxB
PRELIMINARY DATA SHEET
FP Sub- Function
address
Scaler Control Register
h’40
scaler mode register
bit[1:0]
scaler mode
0 linear scaling mode
1 nonlinear scaling mode, ’panorama’
2 nonlinear scaling mode, ’waterglass’
3 reserved
bit[10:2] reserved, set to 0
bit[11]
scaler update
0 start scaler update command,
when the registers are updated the bit is set to 1
h’41
luma offset register
bit[6:0]
luma offset 0..127
ITU-R output format: 57
CVBS output format:
4
this register is updated when the scaler mode register is written
h’42
active video length for 1-h FIFO
bit[11:0] length in pixels
this register is updated when the scaler mode register is written
h’43
scaler1 coefficient, this scaler is compressing the signal.
For compression by a factor c the value c*1024 is required.
bit[11:0] allowed values from 1024..4095
this register is updated when the scaler mode register is written
h’44
scaler2 coefficient, this scaler is expanding the signal.
For expansion by a factor c the value 1/c*1024 is required.
bit[11:0] allowed values from 256..1024
this register is updated when the scaler mode register is written
h’45
scaler1/2 nonlinear scaling coefficient
this register is updated when the scaler mode register is written
h’47 –
h’4b
scaler1 window controls, see table
5 12-bit registers for control of the nonlinear scaling
this register is updated when the scaler mode register is written
h’4c –
h’50
scaler2 window controls see table
5 12-bit registers for control of the nonlinear scaling
this register is updated when the scaler mode register is written
Default
Name
0 scmode
pano
57 yoffs
1080 fflim
scinc1
1024
scinc2
1024
0 scinc
0 scw1_0 – 4
0 scw2_0 – 4
42
Micronas