VDP313XY Datasheet, PDF (39/76 Pages) Micronas – Video Processor Family

ADVANCE INFORMATION
VDP 313xY
Table 2–5: I²C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I²C Sub
address
(hex)
Number Mode Function
of bits
Default Name
(hex)
Analog RGB Insertion
4B
9
wv
4B
9
wv
32
8
w/r
31
8
w/r
bit[7] 0/1
disable/enable analog fast blank 0
input for RGB inserion
bit[0] 0
Picture frame overOSD
0
1
OSD over picture frame
fast blank interface mode
0
bit[0] 0
1
internal fast blank 1 from FBLIN1
pin
force internal fast blank 1 signal
to high
bit[1] 0/1
internal fast blank active high/low
bit[2] 0/1
disable/enable clamping
reference for RGB outputs
bit[3] 1
full line MADC measurement
window, disables bit [3] in
address 25
bit[4] 0/1
horizontal flyback input active
high/low
bit[6:5]
reserved (set to 0)
bit[7] 0
1
internal fast blank 1 from FBLIN1
pin
force internal fast blank 1 signal
to low
fast blank interface mode 2
0
bit[0] 0
1
internal fast blank 2 from FBLIN2
pin
force internal fast blank 2 signal
to high
bit[1] 0
1
internal fast blank 2 from FBLIN2
pin
force internal fast blank 2signal to
low
bit[2]
fast blank input priority
0
FBLIN1>FBLIN2
1
FBLIN2>FBLIN1
bit[3]
fast blank monitor input select
0
monitor connected to FBLIN1 pin
1
monitor connected to FBLIN2 pin
bit[4]
half contrast switch enable
0/1
HCS disable/enable
bit[5]
0
1
half contrast from HCS pin
force half contrast signal to high
bit[6] 0/1
half contrast active high/low at
HCS pin
bit[7]
reserved (set to 0)
ERGB
OSDPRIO
FBMOD
FBFOH1
FBPOL
CLMPR
FLMW
FLPOL
FBFOL1
FBMOD2
FBFOH2
FBFOL2
FBPRIO
FBMON
HCSEN
HCSFOH
HCSPOL
Micronas
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