VDP3108 Datasheet, PDF (11/61 Pages) Micronas – Single-Chip Video Processor

ADVANCE INFORMATION
VDP 3108
2.2.9. Skew Filter
The system clock is free running and not locked to the
TV line frequency. Therefore, the ADC sampling pattern
is not orthogonal. The decoded YC_rC_b signals are con-
verted to an orthogonal sampling raster by skew filter
block at the output of the color decoder.
The skew filters are controlled by a skew parameter and
dB
2
1 parameter: α, 32 steps
0
–1
–2
–3
–4
–5
–6
–7
–8
0
2
4
0.5
0.4, 0.6
6
0, 1.0
0.1, 0.9
0.2, 0.8
0.3, 0.7
MHz
8
10
Fig. 2–11: Luminance, Chrominance skew
filter magnitude frequency response
allow to apply a group delay to the input signals without
introducing waveform of frequency response distortion.
The amount of phase shift of this filter is controlled by the
horizontal PLL1. The accuracy of the filters is 1/32
clocks for luminance and 1/4 clocks for chroma. Thus
the output of the color decoder is in an orthogonal pixel
format even in the case of nonstandard input signals
such as VCR.
clocks
2.5
2.3 _{parameter: α, 32 steps}
2.1
1.0
1.9
0.9 _0.8
1.7
0.7 _0.6
1.5
1.3
0.3 ^0.4
1.1
0.1 ^0.2
0
0.9
0.7
0.5
0
2
4
6
0.5
8
MHz
10
Fig. 2–12: Luminance, chrominance skew
filter group delay characteristics
2.2.10. Picture Bus Color Space
Output of the color decoder block is YC_rC_b with 20.25
Msamples/s. Only active video is transferred. The num-
ber of active samples is 1068 per line for all standards
(525 lines and 625 lines).
The following equations explain the data formats. The
R,G,B source signals are already gamma-weighted.
The transform matrix from R,G,B to color difference sig-
nals is given by:
ǒ Ǔ ǒ Ǔǒ Ǔ Y
R*Y ₊
0.299 0.587 0.114 R
0.701 * 0.587 * 0.114 G
B*Y
* 0.299 * 0.587 0.886 B
In each TV broadcast standard different weighting fac-
tors for (R–Y) and (B–Y) are used:
PAL:
V = 0.877*(R–Y)
U = 0.493*(B–Y)
NTSC:
I = V*cos33° – U*sin33°
Q = V*sin33° + U*cos33°
SECAM: Dr = –1.9*(R–Y)
Db = 1.5*(B–Y)
MAC
Vm = 0.927*(R–Y)
Um = 0.733*(B–Y)
Studio
C_r = 0.713*(R–Y)
(CCIR 601) C_b = 0.564*(B–Y)
In the color decoder the weighting for both color differ-
ence signals is adjusted individually. The default format
will have the following specification:
Y
= 224*Y + 16 (pure binary),
C_r = 224*(0.713*(R–Y)) + 128 (offset binary),
C_b = 224*(0.564*(B–Y)) + 128 (offset binary).
Optionally the picture bus format of the chrominance
components C_r, C_b can be switched to two’s comple-
ment format.
The YC_rC_b FIFO memories allow an adjustable delay for
the video processing e.g. one TV line. The memories are
controlled by the horizontal sync information available in
the front end and the display processor. Using the front
end sync, a window for the active video is generated.
Only active video data are written to the FIFO memories.
The display processor generates the main sync signal
from the display timing and data is read from the FIFOs
using the main sync signal. This allows an adjustable
delay as well as a variable delay, e.g. for VCR timebase
correction.
MICRONAS INTERMETALL
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