BSP3505D Datasheet, PDF (10/40 Pages) Micronas – Baseband Sound Processor

BSP 3505D
3.3. Start Up Sequence: Power Up and I²C-Controlling
After power on or RESET (see Fig. 3–3), the IC is in an
inactive state. The CCU has to transmit the required co-
efficient set for a given operation via the I²C bus. Initial-
ization must start with the MODE Register.
The reset pin should not be >0.45*DVSUP (see recom-
mended conditions) before the 5 Volt digital power sup-
ply (DVSUP) and the analog power supply (AVSUP) are
>4.75 Volt AND the BSP clock is running. (Delay: 0.5 ms
typ, 2 ms max)
This means, if the reset low–high edge starts with a
delay of 2 ms after DVSUP and AVSUP >4,75 Volt, even
under worst case conditions, the reset is ok.
PRELIMINARY DATA SHEET
DVSUP/V
AVSUP/V
4.75
Oscillator
max. 2
RESETQ
0.45 * DVSUP
Fig. 3–3: Power-up sequence
min. 2
time / ms
time / ms
time / ms
Note: The reset should
not reach high level be-
fore the oscillator has
started. This requires a
reset delay of >2 ms
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