MT36LSDT25672G Datasheet, PDF (9/30 Pages) Micron Technology – Synchronous DRAM Module

1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mode Register Definition
Figure 4:
Mode Register Definition Diagram
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12 11 10 9 8 7
Reserved WB Op Mode
6 543
CAS Latency BT
2 10
Burst Length
Mode Register (Mx)
Program
M12, M11, M10 = “0, 0,0”
to ensure compatibility
with future devices.
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
All other states reserved
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.