PF48F4400P0VBQEK Datasheet, PDF (83/95 Pages) Micron Technology – 256Mb and 512Mb (256Mb/256Mb), P30-65nm

256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Table 45: AC Read Specifications (Continued)
Number Symbol Parameter
R200
f_CLK CLK frequency
R201
t_CLK CLK period
R202
t_CH/CL CLK high/low time
R203
t_FCLK/RCLK CLK fall/rise time
Synchronous Specifications⁽⁵⁾
R301
R302
R303
R304
t_AVCH/L
t_VLCH/L
t_ELCH/L
t_{CHQV /}
tCLQV
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
R305
R306
R307
t_CHQX
t_CHAX
t_CHTV
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
R311
R312
t_CHVL
t_CHTX
CLK Valid to ADV# Setup
WAIT Hold from CLK
Easy BGA/QUAD+
TSOP
Easy BGA/QUAD+
TSOP
Easy BGA/QUAD+
TSOP
-
-
-
Easy BGA/QUAD+
TSOP
-
-
Easy BGA/QUAD+
TSOP
-
Easy BGA/QUAD+
TSOP
Min
-
-
19.2
25
5
9
0.3
9
9
9
-
-
3
10
-
-
3
3
5
Max
52
40
-
-
-
3
-
-
-
17
20
-
-
17
20
-
-
-
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1, 3, 5
1, 6
1, 6
1, 6
1, 4, 6
1, 6
1
1, 6
Notes:
1. See on page for timing measurements and max allowable input slew rate.
2. OE# may be delayed by up to t_ELQV – t_GLQV after CE#’s falling edge without impact to
t_ELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is t_CHAX or t_VHAX, whichever timing specifica-
tion is satisfied first.
5. Synchronous read mode is not supported with TTL level inputs.
6. Applies only to subsequent synchronous reads.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
83
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