MT9VDDT6472AG Datasheet, PDF (8/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Burst Length
Read and write accesses to DDR SDRAM devices are
burst oriented, with the burst length being program-
mable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see note 5 of Table 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both read and write bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 3, 2.5, or 2 clocks, as shown in Figure 5,
CAS Latency Diagram, on page 9.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9, indicates the oper-
ating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A11
(128MB), or A7–A12 (256MB, 512MB) each set to zero,
and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A11 (128MB), or A7 and A9–A12
(256MB, 512MB) each set to zero, bit A8 set to one, and
bits A0–A6 set to the desired values.
Figure 4: Mode Register Definition
Diagram
128MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 _{Mode Register (Mx)}
0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
256MB, 512MB Modules
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _{Mode Register (Mx)}
0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
Reserved
M3 = 1
Reserved
2
2
4
4
8
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
2.5
Reserved
M12 M11 M10 M9 M8 M7
0 0 0 0 00
0 0 0 0 10
- - - - --
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
8
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©2004 Micron Technology, Inc.