MT18HTF12872Y Datasheet, PDF (8/18 Pages) Micron Technology – DDR2 SDRAM Registered DIMM (RDIMM)

512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
IDD Specifications
Table 10:
DDR2 IDD Specifications and Conditions – 512MB
Values shown for MT47H64M4 DDR2 SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
Parameter/Condition
Operating one bank active-precharge current: ^tCK = ^tCK (IDD),
t_{RC =} t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid}
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD), ^tRC = ^tRC (IDD), ^tRAS = ^tRAS MIN (IDD),
t_{RCD =} t_{RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address}
bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; ^tCK = ^tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle; ^tCK = ^tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle; ^tCK = ^tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t_{CK =} t_{CK (IDD); CKE is LOW; Other control and address bus}
Fast PDN exit
MR[12] = 0
inputs are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; ^tCK = ^tCK (IDD),
t_{RAS =} t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between valid}
commands; Other control and address bus inputs are switching; Data bus inputs
are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD), ^tRAS = ^tRAS MAX (IDD),
t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus}
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD), ^tRAS = ^tRAS MAX
(IDD), ^tRP = ^tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
Burst refresh current: ^tCK = ^tCK (IDD); REFRESH command at every ^tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = ^tRCD (IDD) - 1 x ^tCK (IDD);
t_{CK =} t_{CK (IDD),} t_{RC =} t_{RC (IDD),} t_{RRD =} t_{RRD (IDD),} t_{RCD =} t_{RCD (IDD); CKE is}
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5
IDD6
IDD7
-53E
1,440
1,620
90
630
630
450
108
720
2,880
2,700
3,060
90
4,320
-40E
1,350
1,530
90
450
540
360
108
540
2,250
2,070
2,970
90
4,140
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
8
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