MT36LSDT12872G Datasheet, PDF (7/30 Pages) Micron Technology – Synchronous DRAM Module

1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
General Description
General Description
The MT36LSDT12872 and MT36LSDT25672 are high-speed CMOS, dynamic random-
access, 1GB and 2GB memory modules organized in x72 (ECC) configurations. SDRAM
modules use internally configured quad-bank SDRAM devices with a synchronous inter-
face (all signals are registered on the positive edge of clock signal CK).
Read and write accesses to SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank; A0–A12, select the device row). The address bits registered coinci-
dent with the READ or WRITE command are used to select the starting column location
for the burst access.
SDRAM modules provide for programmable read or write burst lengths of 1, 2, 4, or 8
locations, or full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
SDRAM modules use an internal pipelined architecture to achieve high-speed opera-
tion. Precharging one device bank while accessing one of the other three device banks
will hide the PRECHARGE cycles and provide seamless, high-speed, random-access
operation.
SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between device banks in order to hide pre-
charge time, and the capability to randomly change column addresses on each clock
cycle during a burst access. For more information regarding SDRAM operation, refer to
the 256Mb or 512Mb SDRAM component data sheets.
PLL and Register Operation
These modules can be operated in either registered mode (REGE pin HIGH), where the
control/address input signals are latched in the register on one rising clock edge and
sent to the SDRAM devices on the following rising clock edge (data access is delayed by
one clock), or in buffered mode (REGE pin LOW) where the input signals pass through
the register/buffer to the SDRAM devices on the same clock.
A phase-lock loop (PLL) on the modules is used to redrive the clock to the SDRAM
devices to minimize system clock loading. (CK0 is connected to the PLL, and CK1, CK2,
and CK3 are terminated.)
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and vari-
ous SDRAM organizations and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I²C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.