JS28F00AP33BFA Datasheet, PDF (54/92 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P33-65nm)

512Mb, 1Gb, 2Gb: P33-65nm
Common Flash Interface
Table 23: Primary Vendor-Specific Extended Query (Continued)
Hex Offset
P = 10Ah
(P+D)h
Length
1
Description
V_PP optimum program/erase voltage.
bits 0 - 3 BCD 100mV
bits 4 - 7 hex value in volts
Note: 1. See Optional Features Fields table.
Address
117:
Hex Code
- -90
ASCII Value
(DQ[7:0])
9.0V
Table 24: Optional Features Field
Address
112:
Discrete
Bottom
Top
–
–
--00
--00
2Gb
Bottom
Top
die 1 (B)
die 2 (T)
die 1 (T)
die 2 (B)
40:
--00
--40
--00
Table 25: One Time Programmable (OTP) Space Information
Hex Offset
P = 10Ah
(P+E)h
(P+F)h
(P+10)h
(P+11)h
(P+12)h
Length
1
4
Description
Number of OTP block fields in JEDEC ID space.
00h indicates that 256 OTP fields are available.
OTP Field 1: OTP Description:
This field describes user-available OTP bytes.
Some are preprogrammed with device-unique se-
rial numbers. Others are user-programmable.
Bits 0-15 point to the OTP Lock byte (the first
byte).
The following bytes are factory preprogrammed
and user-programmable:
Bits 0 - 7 = Lock/bytes JEDEC plane physical low
address.
Bits 8 - 15 = Lock/bytes JEDEC plane physical high
address.
Bits 16 - 23 = n where 2ⁿ equals factory preprog-
rammed bytes.
Bits 24 - 31 = n where 2ⁿ equals user-programma-
ble bytes.
Address
118:
119:
11A:
1B:
11C:
Hex
Code
- -02
- -80
- -00
- -03
- -03
ASCII Value
(DQ[7:0])
2
80h
00h
8 byte
8 byte
PDF: 09005aef845667b8
p33_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. C 12/13 EN
54
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