MT48LC2M32B2 Datasheet, PDF (49/53 Pages) Micron Technology – SYNCHRONOUS DRAM

WRITE – WITH AUTO PRECHARGE ¹
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
DQM 0-3
A0-A9
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m ³
ENABLE AUTO PRECHARGE
BANK
DQ
tRCD
tRAS
tRC
tDS tDH
DIN m
tDS tDH
DIN m + 1
tDS tDH
DIN m + 2
tDS tDH
DIN m + 3
tWR ²
64Mb: x32
SDRAM
T8
T9
NOP
ACTIVE
ROW
ROW
BANK
tRP
DON’T CARE
TIMING PARAMETERS
SYMBOL*
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_{CK (1)}
t_CKH
t_CKS
t_CMH
-5
MIN MAX
1
1.5
2
2
5
1
1.5
1
-6
MIN MAX
1
1.5
2.5
2.5
6
10
20
1
2
1
-7
MIN MAX
1
2
2.75
2.75
7
10
20
1
2
1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
-5
-6
-7
SYMBOL*
t_CMS
t_DH
t_DS
t_RAS
t_RC
t_RCD
t_RP
t_WR
MIN
1.5
1
1.5
38.7
55
15
15
2 ^tCK
MAX MIN MAX MIN MAX UNITS
1.5
2
ns
1
1
ns
1.5
2
ns
120,000 42 120,000 42 120,000 ns
60
70
ns
18
20
ns
18
20
ns
1 CLK+
1 CLK+
ns
6
7
NOTE: 1. For this example, the burst length = 4.
2. Faster frequencies require two clocks (when ^tWR > ^tCK).
3. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
49
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©2002, Micron Technology, Inc.