MT48LC16M4A2 Datasheet, PDF (44/55 Pages) Micron Technology – SYNCHRONOUS DRAM

64Mb: x4, x8, x16
SDRAM
SINGLE READ – WITH AUTO PRECHARGE ¹
T0
CLK
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
T1
tCK
NOP
DQM /
DQML, DQMU
A0-A9, A11
tAS tAH
ROW
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
T2
tCL
tCH
NOP2
DQ
tRCD
tRAS
tRC
T3
T4
T5
T6
T7
NOP2
READ
NOP
tCMS _tCMH
NOP
ACTIVE
COLUMN m³
ENABLE AUTO PRECHARGE
ROW
ROW
BANK
tAC
CAS Latency
tRP
t _OH
DOUT m
tHZ
BANK
T8
NOP
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
SYMBOL*
t_AC(3)
t_AC(2)
t_AH
t_AS
t_CH
t_CL
t_CK(3)
t_CK(2)
t_CKH
t_CKS
MIN
1
1.5
2.5
2.5
6
–
1
1.5
MAX
5.5
–
-7E
MIN MAX
5.4
5.4
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
-75
MIN MAX
5.4
6
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
-8E
MIN MAX UNITS
6 ns
6 ns
1
ns
2
ns
3
ns
3
ns
8
ns
10
ns
1
ns
2
ns
*CAS latency indicated in parentheses.
-6
-7E
-75
-8E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t_CMH
1
0.8
0.8
1
ns
t_CMS
1.5
1.5
1.5
2
ns
t_HZ(3)
5.5
5.4
5.4
6 ns
t_HZ(2)
–
5.4
6
6 ns
t_LZ
1
1
1
1
ns
t_OH
2
3
3
3
ns
t_RAS
42 120,000 37 120,000 44 120,000 50 120,000 ns
t_RC
60
60
66
70
ns
t_RCD
18
15
20
20
ns
t_RP
18
15
20
20
ns
NOTE:
1. For this example, the burst length = 1, and the CAS latency = 2.
2. READ command not allowed or ^tRAS would be violated.
3. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.