M25PX80-VMW6TG Datasheet, PDF (38/56 Pages) Micron Technology – M25PX80 NOR Serial Flash Embedded Memory

BULK ERASE
M25PX80 Serial Flash Embedded Memory
BULK ERASE
The BULK ERASE command sets all bits to 1 (FFh). Before the BULK ERASE command
can be accepted, a WRITE ENABLE command must have been executed previously. Af-
ter the WRITE ENABLE command has been decoded, the device sets the write enable
latch (WEL) bit.
The BULK ERASE command is entered by driving chip select (S#) LOW, followed by the
command code on serial data input (DQ0). S# must be driven LOW for the entire dura-
tion of the sequence.
S# must be driven HIGH after the eighth bit of the command code has been latched in.
Otherwise the BULK ERASE command is not executed. As soon as S# is driven HIGH,
the self-timed BULK ERASE cycle is initiated; the cycle's duration is t_BE. While the BULK
ERASE cycle is in progress, the status register may be read to check the value of the write
In progress (WIP) bit. The WIP bit is 1 during the self-timed BULK ERASE cycle, and is 0
when the cycle is completed. At some unspecified time before the cycle is completed,
the WEL bit is reset.
The BULK ERASE command is executed only if all block protect (BP2, BP1, BP0) bits are
0. The BULK ERASE command is ignored if one or more sectors are protected.
Figure 25: BULK ERASE Command Sequence
0
7
C
LSB
DQ0
Command
MSB
PDF: 09005aef8456659e
m25px80.pdf - Rev. C 1/14 EN
38
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