JS28F128P33BF70 Datasheet, PDF (33/88 Pages) Micron Technology – Numonyx® P33-65nm Flash Memory 128-Mbit, 64-Mbit Single Bit per Cell (SBC)

P33-65nm SBC
11.0.1
Clear Status Register
The Clear Status Register command clears the Status Register. It functions independent
of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.
11.1
Read Configuration Register
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see Section 6.2, “Device Command
Bus Cycles” on page 18).
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see Section 7.3, “Read Device Identifier” on page 21).
The RCR is shown in Table 12. The following sections describe each RCR bit.
Table 12: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read
Mode
RM
15
Bit
15
14
RES
Latency Count
R
LC[3:0]
14 13
12
11
Name
Read Mode (RM)
Reserved (R)
WAIT
Polarity
Data
Output
Config
WAIT
Delay
Burst
Seq
CLK
Edge
RES RES
WP
DOC WD
BS
CE
R
R
10
9
8
7
6
5
4
Description
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
Set to 0. This bit cannot be altered by customer.
Burst
Wrap
BW
3
13:11
10
9
8
7
6
Latency Count (LC[2:0])
WAIT Polarity (WP)
Data Output Configuration
(DOC)
WAIT Delay (WD)
Burst Sequence (BS)
Clock Edge (CE)
000 =Code 0 reserved
001 =Code 1 reserved
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7(default)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
0 =Reserved
1 =Linear (default)
0 = Falling edge
1 = Rising edge (default)
Burst Length
BL[2:0]
2
1
0
Datasheet
33
Jul 2011
Order Number:208034-04