RC28F256P30BFA Datasheet, PDF (32/98 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P30-65nm)

256Mb and 512Mb (256Mb/256Mb), P30-65nm
Read Operations
Synchronous Burst Mode Read
Read configuration register bits RCR[15:0] must be set before synchronous burst opera-
tion can be performed. Synchronous burst mode can be performed for both array and
non-array reads such as read ID, read status, or read query.
To perform a synchronous burst read, an initial address is driven onto the address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been de-asserted.
ADV# is asserted, and then de-asserted to latch the address. Alternately, ADV# can re-
main asserted throughout the burst access, in which case the address is latched on the
next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay. Subsequent
data is output on valid CLK edges following a minimum delay. However, for a synchro-
nous non-array read, the same word of data will be output on successive clock edges
until the burst length requirements are satisfied. Refer to the timing diagrams for more
detailed information.
Read CFI
The READ CFI command instructs the device to output CFI data when read. See Com-
mon Flash Interface for details on issuing the READ CFI command, and for details on
addresses and offsets within the CFI database.
Read Device ID
The READ DEVICE IDENTIFIER command instructs the device to output manufacturer
code, device identifier code, block lock status, protection register data, or configuration
register data.
Table 12: Device ID Information
Item
Manufacturer code
Device ID code
Block lock configuration
Block is unlocked
Block is locked
Block is not locked down
Block is locked down
Read configuration register
General purpose register
Lock register 0
64-bit factory-programmed OTP register
64-bit user-programmable OTP register
Lock register 1
128-bit user-programmable protection regis-
ters
Address
0x00
0x01
Block base address + 0x02
0x05
Device base address + 0x07
0x80
0x81–0x84
0x85–0x88
0x89
0x8A–0x109
Data
0x89
ID (see the Device ID Codes table )
Lock bit
DQ₀ = 0b0
DQ₀ = 0b1
DQ₁ = 0b0
DQ₁ = 0b1
RCR contents
General purpose register data
PR-LK0 data
Factory OTP register data
User OTP register data
PR-LK1 OTP register lock data
OTP register data
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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