MT28C3224P20 Datasheet, PDF (30/42 Pages) Micron Technology – FLASH AND SRAM COMBO MEMORY

ADVANCE
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
TWO-CYCLE PROGRAMMING/ERASE OPERATION
A0–A20 ^VIH
V_IL
V_IH
CE# _VIL
V_IH
OE# _VIL
V_IH
WE# _VIL
V_OH
DQ0–DQ15 _VOL
V_IH
RST# _VIL
V_IH
WP# _VIL
VALID ADDRESS
VALID ADDRESS
t_AS
t_AH
VALID ADDRESS
t_CS
t_CH
t_WOS
t_WPH
High-Z
t_RS
t_WP
CMD
t_DH
t_WB
CMD/
DATA
t_DS
t_RHS
STATUS
t_RHH
t_VPS
t_VPPH
V_IPPH
VPP
V_IPPLK
V_IL
UNDEFINED
WRITE TIMING PARAMETERS
SYMBOL
t_RS
t_CS
t_WP
t_DS
t_AS
t_CH
t_DH
-80/-85
MIN
MAX
150
0
50
50
50
0
0
UNITS
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t_AH
t_RHS
t_VPS
t_WOS
t_RHH
t_VPPH
t_WB
-80/-85
MIN
MAX
1.5
0
200
50
0
0
t_AA+50
UNITS
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle.
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
30
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©2002, Micron Technology, Inc.