M25PX16-VMW6TG Datasheet, PDF (3/56 Pages) Micron Technology – Micron M25PX16 Serial Flash Embedded Memory

M25PX16 Serial Flash Embedded Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 5
Figure 2: Pin Connections: VFQFPN, SO8N ...................................................................................................... 6
Figure 3: Pinout: 24-Ball BGA, 6x8mm .............................................................................................................. 7
Figure 4: Bus Master and Memory Devices on the SPI Bus ............................................................................... 10
Figure 5: SPI Modes ....................................................................................................................................... 10
Figure 6: Hold Condition Activation ............................................................................................................... 14
Figure 7: Block Diagram ................................................................................................................................ 15
Figure 8: WRITE ENABLE Command Sequence .............................................................................................. 19
Figure 9: WRITE DISABLE Command Sequence ............................................................................................. 20
Figure 10: READ IDENTIFICATION Command Sequence ................................................................................ 21
Figure 11: READ STATUS REGISTER Command Sequence .............................................................................. 22
Figure 12: Status Register Format ................................................................................................................... 22
Figure 13: WRITE STATUS REGISTER Command Sequence ............................................................................. 24
Figure 14: READ DATA BYTES Command Sequence ........................................................................................ 26
Figure 15: READ DATA BYTES at HIGHER SPEED Command Sequence ........................................................... 27
Figure 16: DUAL OUTPUT FAST READ Command Sequence ........................................................................... 28
Figure 17: READ LOCK REGISTER Command Sequence ................................................................................. 29
Figure 18: READ OTP Command Sequence .................................................................................................... 30
Figure 19: PAGE PROGRAM Command Sequence ........................................................................................... 31
Figure 20: DUAL INPUT FAST PROGRAM Command Sequence ....................................................................... 32
Figure 21: PROGRAM OTP Command Sequence ............................................................................................. 33
Figure 22: How to Permanently Lock the OTP Bytes ........................................................................................ 34
Figure 23: WRITE to LOCK REGISTER Instruction Sequence ........................................................................... 35
Figure 24: SUBSECTOR ERASE Command Sequence ...................................................................................... 36
Figure 25: SECTOR ERASE Command Sequence ............................................................................................. 37
Figure 26: BULK ERASE Command Sequence ................................................................................................. 38
Figure 27: DEEP POWER-DOWN Command Sequence ................................................................................... 39
Figure 28: RELEASE from DEEP POWER-DOWN Command Sequence ............................................................. 40
Figure 29: Power-Up Timing .......................................................................................................................... 42
Figure 30: AC Measurement I/O Waveform ..................................................................................................... 45
Figure 31: Serial Input Timing ........................................................................................................................ 48
Figure 32: Write Protect Setup and Hold During WRSR when SRWD = 1 Timing ............................................... 48
Figure 33: Hold Timing .................................................................................................................................. 49
Figure 34: Output Timing .............................................................................................................................. 49
Figure 35: V_PPH Timing .................................................................................................................................. 50
Figure 36: VFQFPN8 (MLP8) 6mm x 5mm ...................................................................................................... 51
Figure 37: SO8W 208 mils Body Width ............................................................................................................ 52
Figure 38: SO8N 150 mils Body Width ............................................................................................................ 53
Figure 39: TBGA 24-Ball, 6mm x 8mm ............................................................................................................ 54
PDF: 09005aef845665a5
m25px16.pdf - Rev. A 11/12 EN
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