MT4LSDT1664AG Datasheet, PDF (25/28 Pages) Micron Technology – SDRAM Unbuffered DIMM (UDIMM)

32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Serial Presence-Detect
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions (Continued)
Notes appear below; All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
WRITE cycle time
Notes:
Symbol
Min Max Units Notes
t_WRC
–
10
ms
4
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (^tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle,
the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and
the EEPROM does not respond to its slave address.
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
25
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