MT28S4M16B1LL Datasheet, PDF (25/58 Pages) Micron Technology – SYNCFLASH MEMORY

ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the mode
register to a logic 1. All WRITE commands result in the
access of a single column location (burst of one). READ
commands access columns according to the pro-
grammed burst length and sequence.
Figure 14
HCS WRITE to READ
T0
T1
T2
T3
CLK
COMMAND
WRITE
READ
NOP
NOP
Figure 16
Power-Down
Coming out of a power-down sequence (active),
t_{CKS (CKE setup time) must be greater than or equal to 3ns.}
CLK
tCKS
((
))
((
))
t _CKS
CKE
((
))
((
COMMAND
NOP
))
((
NOP
))
All banks idle
Input buffers gated off
Enter power-down mode.
Exit power-down mode.
ACTIVE
tRCD
tRAS
tRC
Figure 17
Clock Suspend During Write Burst
T0
T1
T2
T3
CK
T4
T5
CKE
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DIN
n
DbOUT
NOTE:
A CAS latency of two is used for illustration.
The WRITE command may be to any bank and
the READ command may be to any bank. DQM is
LOW. For more details, refer to Truth Tables 4
and 5.
Figure 15
Terminating a Write Burst
T0
T1
T2
CK
COMMAND
WRITE
BURST
NEXT
TERMINATE COMMAND
ADDRESS
BANK,
COL n
(ADDRESS)
DQ
NOTE:
DIN
(DATA)
n
DQMs are LOW, and burst
length >1. BURST TERMINATE
command causes data on DQ to
become invalid.
INTERNAL
CLOCK
COMMAND
NOP
WRITE
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
DIN
n+1
DIN
n+2
NOTE: For this example, burst length = 4 or greater, and DQM is LOW.
Figure 18
Clock Suspend During Read Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
DON’T CARE
64Mb: x16, x32 SyncFlash
MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02
25
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©2002, Micron Technology, Inc.