MT32LD3264A Datasheet, PDF (20/27 Pages) Micron Technology – DRAM MODULE

8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
RAS#
V
V
IH
IL
CAS#
V _IH
V _IL
ADDR
V _IH
V _IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
V _IH
OE# VIL
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP
tRP
tCRP
tCSH
tPC tPRWC NOTE 1
tRSH
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCP
tASR
tAR
tRAD
tRAH
ROW
tASC
tCAH
tRCS
COLUMN
tRWD
tCWL
tWP
tAWD
tCWD
tASC
tCAH
COLUMN
tCWL
tWP
tAWD
tCWD
tASC
tCAH
COLUMN
tAWD
tCWD
ROW
tRWL
tCWL
tWP
tAA
tRAC
tCAC
tCLZ
OPEN
tOE
tDH
tDS
VALID
D _OUT
VALID
DIN
tOD
tAA
tCPA
tCAC
tCLZ
tOE
tDH
tDS
VALID
D _OUT
VALID
D _IN
tOD
tAA
tCPA
tCAC
tCLZ
tOE
tDH
tDS
VALID
D _OUT
VALID
D _IN
tOD
tOEH
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
t_AA
t_AR
t_ASC
t_ASR
t_AWD
t_CAC
t_CAH
t_CAS
t_CLZ
t_CP
t_CPA
t_CRP
t_CSH
t_CWD
t_CWL
t_DH
t_DS
-5
MIN
MAX
25
38
0
0
42
13
8
8
10,000
0
8
28
5
38
30
8
8
0
-6
MIN
MAX
30
45
0
0
49
15
10
10
10,000
0
10
35
5
45
35
10
10
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t_OD
t_OE
t_OEH
t_PC
t_PRWC
t_RAC
t_RAD
t_RAH
t_RASP
t_RCD
t_RCS
t_RP
t_RSH
t_RWD
t_RWL
t_WP
-5
MIN
MAX
0
12
12
8
20
47
50
9
9
50
125,000
11
0
30
13
67
13
5
-6
MIN
MAX
0
15
15
10
25
56
60
12
10
60
125,000
14
0
40
15
79
15
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. ^tPC is for LATE WRITE cycles only.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
20
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©1999, Micron Technology, Inc.