MT8HTF6464HDY Datasheet, PDF (16/19 Pages) Micron Technology – DDR2 SDRAM SODIMM

256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
I_DD Specifications
Table 13: DDR2 I_DD Specifications and Conditions – 1GB (Die Revision E and G)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
Parameter
-80E/-
Symbol 800 -667 -53E -40E Units
Operating one bank active-precharge current:^tCK = ^tCK (I_DD), ^tRC =
t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid}
commands; Address bus inputs are switching; Data bus inputs are switching
I_DD01
628 568 468 468 mA
Operating one bank active-read-precharge current: I_OUT = 0mA; BL =
4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRC = ^tRC (I_DD), ^tRAS = ^tRAS MIN
(I_DD), ^tRCD = ^tRCD (I_DD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as I_DD4W
I_DD11
728 548 508 488 mA
Precharge power-down current: All device banks idle; ^tCK = ^tCK (I_DD);
I_DD2P2
56
56
56
56 mA
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle; ^tCK = ^tCK (I_DD); I_DD2Q2 600 520 360 320 mA
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; ^tCK = ^tCK (I_DD); CKE is I_DD2N2 640 560 400 320 mA
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open; ^tCK Fast PDN exit I_DD3P2 320 240 240 240 mA
= ^tCK (I_DD); CKE is LOW; Other control and address bus in- MR[12] = 0
puts are stable; Data bus inputs are floating
Slow PDN exit
80 80 80 80
MR[12] = 1
Active standby current: All device banks open; ^tCK = ^tCK (I_DD), ^tRAS =
I_DD3N2 680 600 480 440 mA
t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between valid com-}
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
I_DD4W1 1288 828 748 668 mA
burst writes; BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS MAX
(I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst I_DD4R1 1308 908 748 668 mA
read, I_OUT = 0mA; BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS
MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:^tCK = ^tCK (I_DD); REFRESH command at every ^tRFC
(I_DD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I_DD52
2240 2160 2000 1920 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I_DD62
56
56
56
56 mA
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
16
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