MT41J128M16HA-125 Datasheet, PDF (149/206 Pages) Micron Technology – Differential bidirectional data strobe

2Gb: x4, x8, x16 DDR3 SDRAM
ACTIVATE Operation
ACTIVATE Operation
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE com-
mand, which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row, subject to the ^tRCD specification. However, if the additive latency
is programmed correctly, a READ or WRITE command may be issued prior to ^tRCD
(MIN). In this operation, the DRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank, but prior to ^tRCD (MIN) with the require-
ment that (ACTIVATE-to-READ/WRITE) + AL ≥ ^tRCD (MIN) (see Posted CAS Additive
Latency). ^tRCD (MIN) should be divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after the ACTIVATE command on
which a READ or WRITE command can be entered. The same procedure is used to con-
vert other specification limits from time units to clock cycles.
When at least one bank is open, any READ-to-READ command delay or WRITE-to-
WRITE command delay is restricted to ^tCCD (MIN).
A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time in-
terval between successive ACTIVATE commands to the same bank is defined by ^tRC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is de-
fined by ^tRRD. No more than four bank ACTIVATE commands may be issued in a given
t_{FAW (MIN) period, and the} t_{RRD (MIN) restriction still applies. The} t_{FAW (MIN) param-}
eter applies, regardless of the number of banks already opened or closed.
Figure 59: Example: Meeting ^tRRD (MIN) and ^tRCD (MIN)
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
CK#
CK
Command
ACT
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
Address
Row
Row
Col
BA[2:0]
Bank x
t_RRD
Bank y
t_RCD
Bank y
Indicates break
in time scale
Don’t Care
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
149
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