MT9VDDT6472AY Datasheet, PDF (14/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 13: IDD Specifications and Conditions – 256MB
DRAM components only
Notes: 1–5, 8, 10, 12; notes appear on pages 18–20; 0°C ≤ T_A ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge; ^tRC = ^tRC
(MIN); ^tCK = ^tCK (MIN); DQ, DM, and DQS inputs changing once per
clock cycle; Address and control inputs changing once every two
clock cycles;
OPERATING CURRENT: One device bank; Active-Read-Precharge;
Burst = 4; ^tRC = ^tRC (MIN); ^tCK = ^tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode; ^tCK = ^tCK (MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; ^tCK = ^tCK
(MIN); CKE = HIGH; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode; ^tCK = ^tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; ^tRC = ^tRAS (MAX); ^tCK = ^tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock
cycle; ^tCK = ^tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle; ^tCK = ^tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle
AUTO REFRESH CURRENT
t_{REFC =} t_{RFC (MIN)}
t_{REFC = 7.8125µs}
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge, ^tRC =^tRC (MIN); ^tCK = ^tCK (MIN); Address and
control inputs change only during Active, READ, or WRITE
commands.
SYMBOL
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD5A
IDD6
IDD7
MAX
-40B
1,215
1,530
36
540
360
630
1,800
1,755
2,340
54
36
3,645
UNITS NOTES
mA 20, 42
mA 20, 42
mA 21, 28, 44
mA
45
mA 21, 28, 44
mA 20, 41
mA 20, 42
mA
20
mA 20, 44
mA 24, 44
mA
9
mA 20, 43
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
14
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©2004 Micron Technology, Inc.