MT4HTF3264HZ Datasheet, PDF (13/17 Pages) Micron Technology – DDR2 SDRAM SODIMM

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM
I_DD Specifications
Table 13: DDR2 I_DD Specifications and Conditions – 512MB (Die Revision H)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
-80E/
Parameter
Symbol -800 -667 Units
Operating one bank active-precharge current:^tCK = ^tCK (I_DD), ^tRC = ^tRC (I_DD),
I_DD0
t_{RAS =} t_{RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus}
inputs are switching; Data bus inputs are switching
320 300 mA
Operating one bank active-read-precharge current: I_OUT = 0mA; BL = 4, CL = CL
(I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRC = ^tRC (I_DD), ^tRAS = ^tRAS MIN (I_DD), ^tRCD = ^tRCD (I_DD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I_DD4W
Precharge power-down current: All device banks idle; ^tCK = ^tCK (I_DD); CKE is LOW;
Other control and address bus inputs are stable; Data bus inputs are floating
I_DD1
I_DD2P
380 360 mA
28
28
mA
Precharge quiet standby current: All device banks idle; ^tCK = ^tCK (I_DD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
I_DD2Q
104 104 mA
Precharge standby current: All device banks idle; ^tCK = ^tCK (I_DD); CKE is HIGH, S# is
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
I_DD2N
120 104 mA
Active power-down current: All device banks open; ^tCK = ^tCK Fast PDN exit
I_DD3P
80
60
mA
(I_DD); CKE is LOW; Other control and address bus inputs are stable; MR[12] = 0
Data bus inputs are floating
Slow PDN exit
40
40
MR[12] = 1
Active standby current: All device banks open; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS MAX
(I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, S# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs are switching
I_DD3N
140 128 mA
Operating burst write current: All device banks open; Continuous burst writes; BL I_DD4W
640
540
mA
= 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read, I_OUT
= 0mA; BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS MAX (I_DD), ^tRP = ^tRP
(I_DD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
I_DD4R
600 500 mA
Burst refresh current:^tCK = ^tCK (I_DD); REFRESH command at every ^tRFC (I_DD) inter-
I_DD5
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
600 580 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
I_DD6
inputs are floating; Data bus inputs are floating
28
28
mA
Operating bank interleave read current: All device banks interleaving reads; I_OUT I_DD7
= 0mA; BL = 4, CL = CL (I_DD), AL = ^tRCD (I_DD) - 1 × ^tCK (I_DD); ^tCK = ^tCK (I_DD), ^tRC = ^tRC
(I_DD), ^tRRD = ^tRRD (I_DD), ^tRCD = ^tRCD (I_DD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
1040 920 mA
PDF: 09005aef83c05a5d
htf4c32_64_128x64hz.pdf - Rev. D 4/14 EN
13
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