MT28C3214P2FL Datasheet, PDF (12/42 Pages) Micron Technology – FLASH AND SRAM COMBO MEMORY

2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
Table 6
Command Descriptions
CODE DEVICE MODE BUS CYCLE
DESCRIPTION
10h Alt. Program Setup First
Operates the same as a PROGRAM SETUP command.
20h Erase Setup
First
Prepares the CSM for an ERASE CONFIRM command. If the next
command is not ERASE CONFIRM, the CSM sets both SR4 and SR5 of
the status register to a “1,” places the device into read status register
mode, and waits for another command.
40h Program Setup
First
A two-cycle command: The first cycle prepares for a PROGRAM
operation, the second cycle latches addresses and data and initiates
the WSM to execute the program algorithm. The Flash outputs status
register data on the falling edge of F_OE# or F_CE#, whichever
occurs first.
50h Clear Status
Register
First
The WSM can set the program status (SR4), and erase status (SR5) bits
in the status register to “1,” but it cannot clear them to “0.” Issuing
this command clears those bits to “0.”
60h Protection
Configuration
Setup
First
Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK
DOWN, then the CSM sets both the program and erase status register
bits to indicate a command sequence error.
70h Read Status
Register
First
Places the device into read status register mode. Reading the device
outputs the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode
after a PROGRAM or ERASE operation has been initiated.
90h Read Protection
Configuration
First
Puts the device into the read protection configuration mode so that
reading the device outputs the manufacturer/device codes or block
lock status.
98h Read Query
First
Puts the device into the read query mode so that reading the device
outputs common Flash interface information.
B0h Program Suspend
Erase Suspend
First
First
Suspends the currently executing PROGRAM/ERASE operation. The
status register indicates when the operation has been successfully
suspended by setting either the program suspend (SR2) or erase
suspend (SR6) and the WSMS bit (SR7) to a “1” (ready). The WSM
continues to idle in the suspend state, regardless of the state of all
input control pins except F_RP#, which immediately shuts down the
WSM and the remainder of the chip if F_RP# is driven to VIL.
C0h Program Device
First
Protection Register
Writes a specific code into the device protection register.
Lock Device
First
Locks the device protection register; data can no longer be changed.
Protection register
(continued on the next page)
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02
12
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©2002, Micron Technology, Inc.